Research And Development On Verification Platform Of Media DSP Processor

The workload of verification increases exponentially as the continuous improvement of IC design automation and chip scale. Usually the RTL code in system increases one more time, while four times or more tasks are needed to verify it. The disadvantage of traditional verification method has been not adapt for nowadays large scale DSP processor. How to cut verification cost and increase verification efficiency has become a challenge.This thesis presents a verification method with two-level platform. The BFM is used to verify each lonely module before system integrating. In the top level, a C++ ISA model is created to verify the entire DSP core. Testcases are written to stimulate both ISA model and HDL model, and bugs can be found quickly thanks to the comparison of two results. The verification method, used in a media DSP processor named Spock(developed by Zhejiang University and C-sky Microsystems Co., Ltd), increase design automation level and save the verification time. The verification platform can be used as a standard environment for DSP verification because of its good reusability.A design of simulator/debugger based on JTAG for DSP processor is also proposed. The debugger realize co-debug (software and hardware debug) as Instruction-Set Simulator is embedded. The instruction run both in hardware and in simulator and the result can be checked on real-time, which increases debug efficiency. The rate of writing memory is increased thanks to hardware-assist download. The debug tools, successfully used in Spock, shorten the debug cycle and give a good example.