Research On Verification IP And Its Application In Verification Platform

With the rapid improvement of silicon ability and design ability, in order to meet the requirement of market for cost, function and power, SoC (System on a Chip) technology has become a developing trend. As all we know, Moore's law (the transistor counts integrated in one chip will be double every 18 months) has always taken place during the evolution process of integrate circuits, thus the scale and function of SoC are expanding rapidly, which makes verification more and more important. Nowadays, verification has become the bottleneck of the whole SoC design process. More and more advanced verification techniques are use to deal with the verification problems of complex SoC system, and are used to detect bugs hidden in the system deeply. Perhaps verification engineers could find most problems of SoC if given enough time. But while limited by time to market, they also need the guide of some effective, time-saving verification methodology.This paper is a part of the National High-tech Research and Development Program (863 Program) "Design and implement of network audio and video signals". The main aim of the paper is to bring forward a design approach of Verification Intellectual Property (VIP) after some discussion and research on popular verification techniques. The VIPs designed under this approach have a high abstract level, and they could be reused in the verification process of one SoC project or several SoC projects. This type of IP could shorten the time of building verification platform, enhance verification efficiency, and solve the bottleneck of verification problem.The paper brings forwards a verification methodology based on high abstract level and multi-layers. We select an IEEE standard hardware language SystemVerilog to implement the methodology because of its specialty. The paper gives emphasis to function and design approach of VIP's components, builds all components into a complete verification environment, and analyzes the design methods of layered verification platform, including principles of components within the platform. At the end of the paper, we construct a bus monitor model, which bases on AMBA2.0 APB bus, and build a verification platform to simulate the performance of the model. The simulation result upon the simulator shows that the bus monitor could really improve the controllability and operability of verification and enhance verification's level.