FPGA Design And Implementation Of Carry Chain Delay Segmentation And Calibration Method

As the basic physical parameters of scientific research,scientific experiments and engineering technology,time provides an essential benchmark for the measurement and quantitative research of all kinematic systems and time series processes.Time contains two concepts of“time”and“time interval”,all of which are closely related to people's daily lives.In satellite navigation,heavy ion accelerators,manned spaceflight and many other high-tech fields,more attention is paid to time intervals,and the requirements for accuracy are getting higher and higher.At present,nanoseconds(10^-9s)or even picoseconds(10^-12s)level have been reached.There are many methods for measuring precise time interval.The Field Programmable Gate Array TDC technology is adopted in a large number of engineering applications because of its high precision,flexible configuration,easy integration,and short development cycle.The core of the method is to implement carry chain delay segmentation and calibration.This topic uses Scale Combination,Wave Union to achieve segmentation and calibration of carry chain delay.The research content includes the following three parts:1.In-depth understanding and detailed analysis of different time interval measurement methods.Through the comparative analysis of several classical methods of precise time interval measurement,it is determined that the carry chain unit inside the FPGA is selected as the delay interpolation unit to realize the precise measurement of the time interval.2.Principle analysis of FPGA carry chain unit delay segmentation and calibration method.The principle of time delay calibration,time delay calculation method and sample size selection of code density method are deduced in detail.Aiming at the defect of large delay unit in the original carry chain of FPGA,the principle of dividing the large delay unit by Wave Union technology is analyzed.A new method of dividing large delay unit by Scale Combination technology is proposed.3.FPGA carry chain delay segmentation and calibration method design,hardware implementation and platform verification.The Cyclone II series FPGA chip is used as the hardware core,and the experimental platform is built to calibrate the original carry-in chain unit delay of the FPGA.The Wave Union and Scale Combination technologies are used to realize the segmentation of the large delay unit of the carry chain,and the segmentation effect is carried out.verification.The data is collected by the internal logic analyzer and processed.The experimental results show that the maximum delay time is reduced from 158.66ps to80.96ps after the Wave Union technology is segmented,and the average delay time is reduced from 57.18ps to 28.25ps.The maximum delay time was reduced from 131.03ps to 62.69ps,and the average delay time was reduced from 64.72ps to 32.21ps.