Physical Implementation Of The Digital Part Of 2 Mega CMOS Image Sensor Chip

Nowadays, with the semiconductor manufacturing technology continuing and the developments of the communication technology, the market of handheld devices such as mobile phones grows at an extraordinary rate. This booms the image sensor industry. Generally, there are two two typical technologies to fabricate image sensors-CCD(Charge Coupled Device) and CMOS(complementary metal oxide semiconductor). CCD technology is mature and its image quality is good thus it is very suit for camera shooting. It’s drawbacks are large power consumption and difficulties to fabricate and integrate with CMOS technology. In contrast, CMOS sensor is easy to manufacture and integrate thus its cost is low. For that reason, CMOS sensors are used intensively in mobile phones and pad. The CMOS sensor industry market is expected to reach $13 billion in 2018.The layout of CMOS sensor is primarily occupied by photodiode array which is analog circuit. Other circuits such as PLL, MIPI, ISP are around the photodiode array. The digital circuit module which is referred to as ISP(image signal processor) is to handle the raw data in order to output image data. Typically, ISP includes lens shading correction defect pixel correction, interpolation, auto white balance, gamma correction, face recognition etc. As people become increasingly demanding on camera’s function, ISP module are increasingly complex. On the other hand, mobile phones and other handheld devices become more compact. This restricts the chip area and bring some challenges to the back-end physical implementation. But the biggest challenges is the rare interconnecting resources because quantum efficiency limits the number of metal interconnecting to 4 layers only.This paper aims to implement the lay out of the digital part of a two mega pixels CMOS image sensor. The difficulties encountered in the implementation process and their solutions are discussed in detail and a brief introduction of the work of the DRC/LVS and formal Verification is made. Our CMOS sensor chip is taped out successfully due to the concerted efforts of the project team.