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Research On Key Technology Of High Speed SAR ADC

Posted on:2019-10-21Degree:MasterType:Thesis
Country:ChinaCandidate:M GaoFull Text:PDF
GTID:2428330626452355Subject:IC Engineering
Abstract/Summary:PDF Full Text Request
ADC,as a bridge connecting digital and analog,is the key module of the receiver front end of wireless digital communication system.Pipeline ADC is widely used in broadband digital communication systems because it can achieve satisfactory compromise among indicators such as resolution,sampling rate,power consumption and area.With the development of advanced semiconductor manufacturing technology,the characteristic size and power supply voltage of the transistor keep dropping,which leads to the small size effect of the device more prominent.SAR ADC is now showing more and more advantages over Pipeline ADC architecture.The high-speed SAR ADC is now expanding to the broadband communication application field,and gradually shows a broader prospect.With SMIC 55 nm CMOS process,this paper have completed the design of 12 Bit 100MS/s SAR ADC.The basic circuit modules include: bootstrap switch,Sub DAC capacitor array,comparator circuit,timing control circuit and reference voltage generating circuit.In addition,a Sub DAC tracking circuit is designed in this paper,which can generate the signal that indicates the Sub DAC capacitor array signal has been established completely.With asynchronous timing,a completely self timing SAR ADC is achieved.At the same time,in order to realize SAR ADC can be more energy efficient under different sampling rates,a reference voltage generating circuit which can adjust power consumption with idle time is designed.Based on the above design,the simulation of the completely self timing SAR ADC circuit is carried out,and finally the layout is realized.The simulation results of the circuit show that when the input signal adopts sinusoidal wave,the power supply voltage is 1.2v,and the sampling rate is 100MS/s,the SFDR of SAR ADC circuit designed in this paper is 80.7dB,SNR is 72.3dB,SNDR is 71.6dB,and ENOB is 11.6Bit.The power consumption self-regulating reference voltage generating circuit can follow the sampling rate for power consumption regulation.
Keywords/Search Tags:ADC, SAR ADC, Completely self timing, Reference voltage generator circuit
PDF Full Text Request
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