Buffer Designs For High-radix Router Basing On STT-RAM

Nowadays,in datacenters and future exascale computers,there is a distinct trend to build networks from many thin links rather than fewer fat links which motivates the utilization of high-radix routers.Building a network using high-radix routers with many narrow ports can reduces the diameter of network,reduces the latency,reduces the cost of building a network and greatly increases the reliability of network.Besides,the interconnection paths between nodes will be more flexible and the network throughput will be increased.However,the development of high-radix router still faces many challenges,.How to design and manage the buffer structure is always the bottleneck of designing high-radix router.In recent years,the widespread use of NVMs have brought hope to solve this bottleneck.High-density and low-leakage STT-RAM is considered to be the most likely to replace traditional SRAM.In our design,we propose a centralized buffer design with STT-MRAM for row buffers based on YARC.We move all the row buffers to its upstream input port and reorganize them into a single STT-RAM bank as a centralized row buffer,and we further improve the performance of this centralized row buffer by using Dynamically-Allocated Multi-Queue(DAMQ).The result shows YARC+STT1-DAMQ can achieve 16.4% performance improvements in saturation injection rate than YARC under uniform.By integrating multiple ports into a single tile,MBTR router can save large reduction in area consumption than YARC router.We also propose a centralized buffer design with STT-MRAM for input buffers based on MBTR,and further organise input buffers in the same tile as a centralized input buffer using STT-MRAM and organise the centralized input buffer as a buffer pool to increase the buffer utilization.The result shows CIMBTR and CIMBTR+STT1-DAMQ can achieve 6.67%,19.0% performance improvements in saturation injection rate than MBTR under uniform.