Research Of Micro-Controller Based On RISC-V Instruction Set

In this era of digital information,electronic products such as mobile phones,computers and smart homes are inseparable from people's lives.These intelligent products will basically have a core chip called microcontroller.The microcontroller,together with other peripherals and interfaces,constitutes a microcontroller to realize different functional control of various intelligent electronic products,so as to ensure that electronic products serve people in the fields of industry,national defense,communication and transportation.The performance optimization of the processor can improve the speed of the whole process,so it is of theoretical and practical significance to study the controller and optimize the design.Based on risc-v instruction set,this paper studies the controller in risc-v processor.The main work is as follows:First,Analyze the architecture of risc-v instruction set.Based on the common instructions in risc-v instruction set,this paper compares and analyzes the characteristics of risc-v instruction set,and makes full use of the advantages of simplicity and simplicity of this instruction set to complete the design of risc-v microcontroller structure.Second,A 32-bit microcontroller with multi-level pipeline is designed to implement 47 basic instructions in risc-v,including basic operation instructions,jump instructions and transfer instructions.In this processor,the basic structure of five level pipeline bit and the static prediction mechanism are adopted,and the branch delay slot technology used in the classic RSIC processor is abandoned.At the same time,a uniform and accurate synchronous exception handling method is adopted,and the pipeline cavitation method is adopted.In the implementation of interrupt and exception processing,the processing time of one clock cycle is sacrificed to reduce the hardware resource overhead due to separate processing of precise synchronous exception and imprecise asynchronous exception.Third,Through the interconnection of wishbone bus and controller,SDRAM controller is designed.The SDRAM controller uses the parameterized design method,which can realize the compatibility of different SDRAM controllers by changing the input parameters.At the same time,the core controller and the bus controller are designed in a modular way,which is convenient for the interconnection of other buses.Fourth,The focus verification method is used to verify the designed microcontroller.This verification uses Modelsim software to build the verification environment,and completes the verification of the microcontroller in logic,shift and arithmetic instructions.At the same time,the designed microcontroller is downloaded to FPGA for verification,and the verification results meet the expected requirements.