High Code Density Of Risc Architecture Microcontroller Design And Implementation

It is mentioned widely that CISC architecture has highly instruction consistency but RISC architecture has efficiently instruction execute. On the design of the morden Microcontroller, how to combine the two merit is one of the hotspots about the research of the system architecture.This paper focuses on the RISC (Reduced Instruction Set Computer) architectural Microcontroller, emphasis on the 8 bit MCS51 Microcontroller . We want to design and implementation of instruction set compatible with MCS51 Microcontroller.The key of the RISC 51 IP CORE system is the architectural design and implementation of instruction set compatible with MCS51 Microcontroller. Following describing the system's organisation ,We discuss the design and implementation of the system in detail including data paths,ALU .To design the control paths ,we start with the analysis of MCS51 instruction set ,and then discuss the instruction execution procedure instruction and operation ,and schedule of instruction timing.The content of the thesis is listed below:1. Design microcontroller's architecture from system level, partition functional modules and define interfaces between each other;2. Design the data path of the RISC 51 IP CORE .emphasis on the Arithmetic Logical Unit;3. Design the control path of the RISC 51 IP CORE to make the RISC 51 IP CORE'S instruction set compatible with MCS51 Microcontroller;4. Develop the simulation environment for full-instruction simulation of the Microcontroller;The result of this paper shows that user RISC CORE method to design the Microcontroller is an efficiently way to improve the system performance.