Research And Design Of GCC Toolchain Of RISC-V Microcontroller With Extended Multiply-Add Instruction

Based on the RISC-V architecture with the characteristics of simplicity,open source,modularity and so on,the designed microcontroller has low power consumption,and is very suitable for embedded application development.The demand for versatility and computing power of the microcontrollers is growing with the application of embedded technology in the Internet of Things,Artificial Intelligence,self-driven car,etc.The function of computing power in RISC-V microcontrollers need to be expanded to meet the operation performance of real-time computing,operational precision,instruction parallelism,etc.Due to the limitation of intellectual property rights,commercial software tools cannot be directly applied.When the software and hardware development platform with the core of RISC-V microcontroller is provided to the user,a corresponding compiler tool chain should be developed.Therefore,it has more practical meaning and wide application prospect to quickly develop a set of efficient customized compiler tool chain and maximize the performance of RISC-V microcontroller in the embedded cross-development environment with the flexible expansibility of RISC-V and the open structure advantage of GCC tool chain.In this paper,a set of GCC tool chain for RISC-V microcontrollers with extensions multiply-add instructions was researched and designed including 32-bit riscv-none-embed-gcc(compiler),riscv-none-embed-as(assembler)and riscv-none-embed-ld(linker)to meet the needs of computing power and embedded cross-development of RISC-V microcontroller for computation-intensive applications.First,basic structure of the compiler(gcc),assembler(as),linker(Id)in the GCC tool chain,and the RISC-V architecture instructions and data characteristics were analyzed.The gcc back-end migration mechanism and the assembly code generation process were proposed.The gcc compiler and the BFD library were transplanted.The assembly and link porting interface were designed.The 32-bit executable programs of riscv-none-embed-gcc,riscv-none-embed-as and riscv-none-embed-ld were generated.The compilation and error reporting functions of riscv-none-embed-gcc,the identifing normal commands and reporting abnormal commands functions of riscv-none-embed-as and the parsing undefined symbol and relocating the correct address functions of riscv-none-embed-ld were tested and verified respectively by the objdump disassembly tool,DejaGnu professional test tool and readelf tool.And the GCC tool chain design of the RISC-V microcontroller was quickly designed.Then,the assembly format of the fixed-point multiply-add instruction was designed.The basic method of the extended operation type conversion rule was proposed.The mapping of the instruction expander to the irregular multiply-add instruction was completed.And the C test case with mixed data types was designed to test the compiler extended multiply-add instruction.The madd and mixmadd instructions can be generated correctly by the compiler,and can be recognized correctly by the assembler.The function of the riscv-none-embed-gcc backend and riscv-none-embed-as for regular and irregular fixed-point multiply-add instructions were realized.The GCC tool chain supporting fixed-point multiply-add instructions was designed.Finally,a shifted and simplified instruction matching template was designed by the weakened peephole optimization method in view of the high CPU computational cost in the RTL intermediate code generation process.The shift operation in data-intensive applications was optimized,and the peephole optimization for riscv-none-embed-gcc supporting fixed-point multiply-add instructions is completed.The target file volume after compiling four data-intensive programs was tested by the objdump tool to verify the peephole optimization effect.The overall performance of riscv-none-embed-gcc was compared and evaluated by the SPECCPU2017 professional test set.The results show that the target file size with peephole optimization is reduced by about 11%of the average,that the compilation performance of data-intensive programs is improved for the riscv-none-embed compiler with extended multiply-add instructions,that the ratio is about 20%,and that the performance improvement ratio for computationally intensive programs such as image processing is about 50%.The GCC tool chain designed in this paper can assist the testing of hardware design and the development of upper-level applications.The compiled target code is small in size.The storage space of the microcontroller effectively saved.It can be applied to wearable devices,home gateways and other small size and low power consumption,and be suitable for computing-intensive applications and data-intensive applications such as image processing,supercomputers,e-commerce systems.