A Research On Cache Replacement Mechanism For Hybrid Memory Systems

Caches play a very important role in the memory hierarchy. It can greatly bridge the gap between the performance of the slow main memory and that of the fast processor, significantly improving the performance of the system's memory access. To better manage the cache, two kinds of cache management policies have been proposed. One aims at the miss count reducing and the other one aims at the miss penalty reducing. However, both kinds of policies are proposed based on the traditional main memory. With the emergence of the hybrid memory, the latency of accessing PCM is several times higher than that of accessing DRAM on a cache miss. It challenges us to optimize the cache management policy in hybrid memory systems.This paper presents a novel miss penalty aware cache replacement mechanism called MALRU for hybrid memory systems. Based on the latency of accessing the main memory, cache blocks are classified into two categories: high latency blocks and low latency blocks. By the method of runtime sampling, statistical information about the reuse distance of two kinds of blocks is obtained. The statistical information is fed to a computing model built by MALRU to partition the optimizable interval. On a cache block replacement, low latency cache blocks at the optimizable interval are prioritized as victims. If high latency blocks encounter a cache miss, the system will have to bare high miss penalty. MALRU actually expands available space for high latency blocks to increase their hit ratio.To verify our cache replacement mechanism, we compare our MALRU mechanism with LRU policy based on the SPEC CPU 2006 benchmark suit. The experimental results show that MALRU improves the system IPC by up to 8.5%.