| Performance of the CPU is directly connected with the cache memory performance as CPU directly interacts with the cache. The performance of the cache depends on the hit/miss ratio, which in turn depends on the data stored in the cache. Data in the cache is controlled by the replacement policy.; In the conventional design, the control unit of the cache is external to the cache. This induces some delay in routing the control signal to the cache. The main concern of the proposed design is to reduce this delay.; In the proposed design, the control is part of the cache memory thus eliminates routing delay and speeds up the replacement policy. Thus by reducing the control signal routing delay, performance of the memory and the computer can be improved. |
