The Realization Of Embedded CPU Memory Management Unit

This thesis studies the memory management unit (MMU) of the central processing unit (CPU). The MMU is the key unit to control the various memory accesses. The functions of the MMU are to control the various memory systems, translate the virtual addresses into physical addresses and control the access permission.The MMU is implemented by the principle of the pagination management and translation of the virtual-to-physical addresses. To further enhance the performances of the MMU, this paper designs translation lookaside buffer (TLB) and system control coprocessor (CP15). The TLB is used to memory the addresses of sections and pages and CP15 is for the control of the standard memories and systems equipments.The modules are used to implement the MMU by VHDL languages. To test the performances of the MMU, this paper designs a test scheme by PERL language. The developed MMU passes the test and its feasibility and Tightness are verified.