CNT-Cache: An Energy-Efficient Carbon Nanotube Cache With Adaptive Encoding

With the rapid development of computer technology,power consumption has become a limiting factor that hinders the scaling of multi-core processors.And Solving it is of vital importance to the design and manufacture of future high-performance processors.In a processor,cache remains the major source of the power consumption despite the evolvement of the processors.For example,cache in Alpha 21264,Strong ARM,Niagara and Niagara-2 accounts for 16%,30%,24% and 24% of the total power consumption[2][3].Thereby,improving the energy efficiency of the cache is critical to detour the power wall challenge of the large-scale multi-core processor design.In recent years,the CMOS Carbon nanotube field effect transistors(CNFET)emerge as a promising alternative to the conventional CMOS for the much higher speed and power efficiency.However,the current CNFET-based SRAM design has a reading and writing power consumption deviation on 0/1 : the power consumption of reading 0 is about 3 times that of reading 1,and writing 1 consumes about 10 times as much power as writing 0.Which bring huge power loss to CNFET-based cache designs.In order to maximize the potential of CNFET-based Cache,we developed a CNT-Cache,each part of the cache can run with lowest power consumption,and the overall power consumption of cache can be significantly descented.The asymmetry of 0/1 in CNFET-based SRAM cells causes serious data correlation,witch indicates that the dynamic power consumption of cache is directly related to the 0/1 distribution in the stored data.For on-chip Cache,we use this 0/1 asymmetry of power consumption and data correlation to proprse a cache design that provides adaptive data encoding.Among them,considering that the read and write operations have opposite power consumption advantages to 0/1,this data encoding strategy requires real-time access mode(Read Intensive or Write Intensive)prediction to ensure the validity of the data encoding.The experimental results show that compared with the traditional CNFET-based Cahce design,the power consumption of our proposed cache optimized to provide adaptive data coding is reduced by an average of 8%.