Design Of Output Buffer Circuit With PVTL Compensation Technique

The traditional output buffer provides vital signal channel for each module in circuit system,but it is only suitable for modules with same supply voltage.For completing the signal transmission between the chips fabricated by different processes,the traditional output buffer has been replaced by the stacked mixed-voltage output buffer.Meanwhile,in order to satisfy some high-speed systems demand,its main research trend is low slew rate(SR)deviation,high data rate,low power consumption.In the proposed technique,all-process-corners detectors need several clock cycles and cannot avoid possible error code compensation,the leakage current compensation circuits cannot effectively compensate power consumption and SR.Besides,the voltage level convertor(VLC)in output stage owns single charging path,it takes more time to charge the output to a stable state at 2×VDD mode,which causes slow data rate.Firstly,to enhance SR compensation performance in PVT(Process,Voltage,Temperature)variations and improve data rate,this thesis presents a novel mixed-voltage output buffer using PVT encode compensation technique.The process detector is composed of four MOS transistors,which can classify all five process corners during one clock cycle,and the structure is simple.Moreover,the compensation logic code can be ensured unchanged in VT variations,which is helpful to avoid error code compensation.Besides,the charging paths of the VLC proposed in this thesis are independent at the two VDDIO modes and directly driven by logic gates.After applied in output stage,the simulation results show that the maximum data rate can reach 800 MHz at VDDIO = 1.2/2.5V.Secondly,this thesis presents a leakage current compensation circuit based on the PVT compensation,which consists of a stacked inverter,CMOS transmission gate,and two switch MOS.When the output voltage is detected to be stable,the logic code generated by the compensation circuit can turn off corresponding driving MOS to decrease leakage current and power consumption.The simulation results show that the leakage in output stage is reduced by 2.91/2.87 times compared with the PVT compensation at VDDIO = 1.2/2.5V under 100 MHz data rate,SS corner,and 100?,respectively.Then,the proposed output buffer in this thesis is implemented using TSMC 90 nm 1.2V 1P9 M CMOS process,and the core area is 0.022mm2.After the chip samples were packaged,chip measurement was performed.The measured results show that the maximum data rate is 640/480 MHz at VDDIO = 1.2/2.5V,the dynamic power consumption is 32.2m W when the data rate is 640 MHz.With PVT compensation,the slew rate is increased by 41.5%/41.9%,respectively.According to the signal eye diagram,the eye height is increased from 0.685/1.775 V to 1.447/2.323 V,respectively.Finally,the measured results prove that the proposed PVTL compensation technique and VLC in this thesis can reduce SR deviation range and increase data rate.There are also problems with output impedance mismatch,layout trace coupling,inductance effects,which wish to be resolved in future designs.