Design Of ZYNQ-based Sled Test Data Acquisition System

The sled test data acquisition system is the key equipment for dynamic parameter testing of a certain type of radar.This thesis simulates the actual test conditions of the missile-borne radar system through the sled test.Based on this,a set of compatible high-speed communication buses is designed,which has multi-channel data acquisition,high-speed data transmission,large-capacity data access functions,and can withstand data recording equipment for 11 g overloaded radar simulation experiment.It is combined with remote control power supply and distribution remote control equipment to form a sled test data acquisition system.After summarizing the functional requirements and technical indicato RS-of the project,the system design is divided into two parts: hardware design and software design.After the design is completed,the system is partially functionally simulated and tested.The system hardware consists of four boards.The core control board in the data recording equipment is equipped with the ZYNQ chip as the core controller of the entire data recording system.The high-speed data communication board design the system high-speed data communication module,it inclueds optical fiber communication,DDR SDRAM cache and multi-channel gigabit ethernet communication.At the same time,the main control peripheral auxiliary circuit and system power supply module are also on this board.Serial communication and data acquisition board includes serial communication circuit,analog acquisition module,DDR cache module,CF memory module and other interface circuits.The serial communication circuit includes LVDS communication,RS-485 communication,etc.The remote power distribution board realizes the functions of remote control,system power distribution and power-off delay.The system software is mainly composed of firmware logic development and application software design.The firmware logic is ZYNQ PS and PL main control communication logic for PS and PL data interaction;RS-485 communication logic and RS-232 are introduced in serial communication logic Communication logic,etc.In addition,there are 20 analogue acquisition logic,PL DDR SDRAM cache control logic and CF card storage logic design.The driver is based on the multi-core ZYNQ interrupt and shared memory to achieve the design of mul ti-channel Gigabit Ethernet communication interruption to meet the system requirements of the multi-network port data transmission function..Finally,this thesis carried out part of the hardware and logic simulation of the designed the sled test data acquisition system.At the same time,the hardware and software tests were carried out using the existing equipment conditions.In the hardware simulation,the structural mechanics simulation and the high-speed signal integrity simulation of the high overload protection shell are performed.The logic of the design is partial communication function logic and storage logic simulation.In the hardware test,some functional tests are mainly performed on the board.And in the software test,the transceiver function of the ethernet link and the system speed index are mainly tested,its single port has an average communication rate of 800 Mbps.The main functions and performance indexes of the system meet the design requirements.