The Design Of H.265 Video Encoding System Based On FPGA

H.265/HEVC is a new-generation video codec standard,mainly used for high-definition and ultra-high-definition video.Compared with the previous generation H.264,H.265 is based on H.264 and retains some of the original technologies.At the same time,it is improved to improve the compression rate and encoding quality,and at the same time double the video bit rate.However,the H.265 encoding algorithm has a high computational complexity and requires very strong computing power to complete the real-time encoding and decoding of the video.However,the software solution causes a very low throughput and it is difficult to meet the real-time encoding requirements.Therefore,combining FPGA with H.265 encoding technology can make full use of the advantages of FPGA parallel processing and flexible access of IP cores,Thus effectively improving encoding performance and speed.This article takes the H.265 video codec standard as the research object,and designs FPGA-based hardware for the intra and inter prediction modules with high complexity in H.265 encoding.Aiming at the problem of poor coding performance of the coding system implemented by the traditional embedded processor,this paper proposes a design scheme of the H.265 coding system based on the Zynq platform,make up for the shortcomings of traditional coding systems.The main research contents of this paper are as follows:1.This article analyzes the structure of the H.265 coding standard in depth,and studies the implementation process of H.265 video coding.For the many intra prediction modes and the complicated division levels,it leads to too many combinations of traversal division and prediction modes,resulting in calculations.The problem is very large.This article uses the basic block as the hardware multiplexing structure of the processing unit,and can support the prediction of all modes.Parallel coding can effectively reduce the coding time.For the high computational complexity of the motion estimation algorithm during the inter prediction process Based on the traditional TZSearch algorithm,this paper proposes an algorithm improvement and hardware design based on FPGA to speed up the processing speed of the system during the motion estimation process.2.Aiming at the low speed,low integration and high power consumption of traditional coding systems,this paper proposes a solution based on Zynq.Designed the H.265 encoding IP core,data cache and packaging module design based on AXI-Stream interface,and completed the drive design of camera acquisition and encoding IP core on Zynq7020 platform,and finally completed the whole set of video collection,display,encoding And storage coding system.The experimental results show that the system can stably realize the real-time encoding transmission of 1920 × 1080 P @ 30 fps HD video.