Research On An Addressing And Operation Storage Integrated IP Core Based On FPGA

The use of FPGA has the operating characteristics of parallel execution,aiming at Multi-floating operand arithmetic controller with dual channel data transmission in the ARM+FPGA architecture PLC system,an addressing and operation storage integrated IP core,which is used to organize and transmit arithmetic operations,is designed.The integrated IP core,which can be used to achieve access to memory and register-file by multiple addressing modes,provide arithmetic operations for arithmetic controller.The main achievements of the research are as follows:(1)Based on the analysis of multi-floating operand arithmetic controller with dual channel data transmission of the basic functions and interface information,determine the main function of addressing and operation storage integration IP core,puts forward the research idea and design scheme,completed the internal structure of IP core,complete the instruction design of various addressing modes.The design of the interface circuit of the IP core respectively with the FPGA central controller and the multi-floating operand arithmetic controller with dual channel data transmission.(2)The instruction buffer module is designed.The instruction buffer module can realize the storage of the instructions from the central controller.The instruction cache module can be used to store the instructions transmitted by the central controller for the main controller.The process of receiving the instruction transmitted by the central controller and the addressing process of the IP core internal operand can be executed in parallel.(3)The main controller of IP core is designed.The main controller controls the data stream and the address stream of the memory and the register-file,and can independently complete the addressing of operands in multiple addressing modes.The main controller can independently control the source address,source operand and destination address,and the source operand is stored in the destination address,the source operand addressing process and destination operand addressing process can be executed in parallel.The process of receiving the instruction transmitted by the central controller and the addressing process of the internal number of IP cores can be executed in parallel.(4)The register-file is designed,which are composed of two parts,the register-file consists of 32 32-bit registers and the register–file controller.And the register-file controller consists of three independent groups of read/write controller,the three groups of independent read/write controllers are respectively responsible for the read and write control of the main controller,the read only control of the arithmetic controller and the processing of the write operation of the result register.In this paper,the control process of data transmission is described,and the flow charts of the main controller read and write register-file and arithmetic operator read register-file is given.(5)The memory is designed.Memory is designed as main memory and Cache,aiming at the address mapping rules and page replacement strategies for Cache,two modules were designed,which were named CAM and MMU.CAM work for the address mapping,MMU work for page replacement.The CAM module realizes the address mapping process according to the control signal of the main controller,and the MMU module processes the change of the storage address and the content of the storage space in real time to realize the address stream and data stream processing.(6)Based on the Libero IDE v8.3 integrated development environment of Actel company,each module and verification procedures is designed.Through the simulation test and test on FPGA,we can see that the integrated IP core can realize the function of addressing and operation storage.