Research On Sequences And Execution Mechanisms Of Multi-operand Four Mixed Operation Instructions

With the continuous improvement of the operational accuracy requirements of actual process data such as speed,temperature,frequency,and voltage in industrial process control,the application of floating-point arithmetic becomes more extensive.This project uses FPGA to research floating-point operations and data storage in the execution of the PLC system,propose a multi-operand four mixed operation instruction execution mechanism thinking.According to this execution mechanism,design a multi-floating operand four mixed operation instruction sequence and operation execution controller,the controller can achieve the transfer storage of floating-point operands and single/double-precision floating-point operations.The main achievements of the project research are as follows:(1)Complete the design of four mixed operation instructions for floating-point operands.According to the operation requirements,the operation instruction is designed to be 32 bits,and the instruction format is divided into operation operation code,operand number,data source mode,rounding mode and single/double precision 5 items.And based on the operand transfer requirements,a 32-bit operand transfer instruction was designed,the instruction contains information such as the type of addressing,the number of operands,whether it is used for operations and addressing addresses,etc.(2)Propose an FPGA-based implementation mechanism for multi-operand four mixed operations.According to the control requirements of the floating-point operand arithmetic process,operand storage and transfer process,the overall structure of the arithmetic execution controller is designed and divided into two parts,operation operand memory controller and arithmetic operation controller.Under the action of the operation operand transfer instruction,the operation operand storage controller completes the storage and transmission of the floating-point operation operand,and the arithmetic operation controller completes the operation under the operation instruction.(3)The internal structure design of the operand memory controller is completed,divide into four modules: instruction cache,main control,memory and register file.After receiving the operand transfer instruction from the FPGA controller,the controller can organize floating-point operation operands,and sent the data to the data channel of the arithmetic operation controller for it to take part in the operation.(4)The internal module construction of the floating-point arithmetic operation controller is completed,divide into six modules: provisioning control,floating-point operation,data allocation,accumulator,queue and result flag registers.After receiving the operation instruction,the controller can autonomously complete four kinds of operation functions of addition,subtraction,multiplication,and elimination in different modes.After the operation is completed,the result can be written to the system data bus by an arithmetic operation controller or an operand memory controller and then read bythe FPGA controller.(5)Design operation execution controller by using Altera's Quartus II 11.0programming software.Operation operand storage controller in operation execution controller are verified on the Cyclone IV EP4CE115F23I7 N chip,and a serial port verification scheme is designed and illustrated.The operation execution controller and internal modules are verified by simulation.From timing simulation and board-level verification,it can be seen that the operation execution controller can achieve its function.