The Research And Implementation Of Efficient Error Correction Technology For On-chip Memory

With the rapid development of aerospace application requirements,spatial information processing puts forward higher requirements against the performance of irradiated on-board integrated circuit chips.With the continuous development of semiconductor technology,the feature size is shrinking,and the performance and integration of integrated circuits are multiplied.At the same time,the probability of unit flip and multi-bit flip events on the on-chip memory cells is greatly increased,which has become the main source of soft errors for the current high-performance micro-processing and SOC(System on Chip).On-chip SRAM memory occupies most of the chip area,so the performance and reliability design of on-chip memory is important for designing high-performance microprocessors.This paper focuses on the EDAC coding technology of on-chip memory and efficient hardware implementation.It can quickly and efficiently realize the EDAC reinforcement design of various memory cells on the chip,and has important theory and engineering to improve the design efficiency of radiation-resistant high-performance microprocessor.It can quickly and efficiently realize the EDAC reinforcement design of various memory cells on the chip,and has important theory and engineeringapplication value to improve the design efficiency of radiation-resistant high-performance microprocessor.The main work and innovations of this paper are reflected in the following aspects:1?An algorithmic optimization is performed on the construction of the single error correction-double error detection(SEC-DED)check matrix,which reduces the probability of adjacent two-bit error,and simultaneously the hardware circuit design implements an configurable IP template for this code parameters.2?The function and performance optimization of an on-chip memory bank based on SEC-DED design has been greatly improved,which has greatly improved the memory in terms of data reading,small granularity writing,number of background buffers and busy signal setting withthe hardware overhead greatly reduced.3?A pruning search check matrix generation algorithmbased on a single error correction,double error detection,and double adjacent error correction code(SEC-DED-DAEC)is proposed.The algorithmmainly used the core idea of pruning and pseudo-greedy which can completely eliminate the adjacent two errors.Using C language,all parity check matrices with 8-512 bits of information bit width satisfying SEC-DED-DAEC error-free rate are generated on Matlab.4 ? Using Python language to integrate the hardware circuit design of SEC-DED-DAEC code into a parameter configurable template,which can automatically generate RTL design code and test module for the required type of memory component reinforcement,so that the on-chip memory components with different bit widths Both can achieve SEC-DED-DAEC hardening and correction.5?There are many parameters such as the port type,data width,depth,and refresh of the on-chip memory components.The reinforced layer module written by different designers can easily lead to diversified styles,thereby further increasing the workload of verification.Using Python Tkinter to integrate the storage reinforcement based on EDAC algorithm,designing the graphical interface of human-computer interaction visualization and file reading parameters,which can directly provide the RTL design code and verification platform for the designer's required component reinforcement,greatly improving the efficiency of automatically generating RTL code reduces the amount of work required for code design and verification.Finally,the above EDAC algorithm based on memory hardening design is applied to the VX-DSP microprocessor chip,which accelerates the progress of the project and ensures the stability of the engineering system.