Construction Of Low Density Parity-Check Code With Low Cyclic Complexity And Implementation With FPGA

Low Density Parity-Check Code,known as LDPC code,is a kind of linear block codes.The key idea of LDPC is to make the information scattered throughout the whole bit code.Then,in the decoding process,the error information is also scattered.As a result,the error rate gets reduced.This property makes LDPC code gain Shannon-limit-approaching performance.Recently,researches on the LDPC code gets maturer and maturer and LDPC code starts to be applied in many areas such as deep space communication,optical fiber communication,mobile communication,underwater communication and even storage.There are several factors which may affect the performance of LDPC code.The girth,length,minimum distance and cyclic distribution are consisted.As QC-LDPC code has shown a good performance on these factors and it's easy to be implemented,it has been one of the most widely used LDPC codes.Recently,the LDPC code based on affine permutation matrix has been attracted because of some advantages rather than QC-LDPC code in minimum-distance,cyclic distribution and error-rate performance.The main works of this paper are as follows:Firstly,with the researches on the LDPC code,presentations and some methods on coding and decoding which are commonly used are described.Then further studies and comparisons between the QC-LDPC code and the APM-LDPC code have been made.After some presentations and properties of the permutation matrices and the parity-check matrices,conditions whether the cycle in specific length in the parity-check matrix exists are explored.Then effective construction methods of parity-check matrices are proposed and simulated for the two kinds of LDPC codes.Later a new idea of permutation matrix construction is proposed which leads to a new kind of permutation matrices come out.Based on it,a new kind of parity-check matrix is obtained.After some researches on the properties of the new parity-check matrix,an effective method which can construct parity-check matrix with fixed girth is proposed.It's proved to be right in the later work.Then followed with simulations by Matlab,the properties of the new parity-check matrix are studied and compared with the former two kinds of parity-check matrices.Finally,the new-proposed LDPC codes are implemented on FPGA.Designs of the encoder are made.The functions of the modules are pointed out.Then the output data of the encoder is verified by simulation.Then the codewords are sent to the decoder and the results of the encoding are obtained.