Research On Flash Error Characteristics Aware Optimization Methods Of Low-Density Parity-Check Codes

The improvement of flash manufacturing technology,the use of multi-bit technology,and the development of three-dimensional stacking technology have improved the storage density and capacity of flash memory,but the reliability of data storage is threatened.To ensure the reliability,low-density parity-check?LDPC?codes with the higher error correction capability have been widely used.Especially with the popularity of three-dimensional stacked flash memory,LDPC codes have become an effective technical means to gurantee the reliability.However,the direct use of the traditional LDPC codes increases the read latency of flash memory due to the increasing of raw bit error rates?RBER?.On the one hand,LDPC codes with soft decision decoding characteristics need to obtain soft decision log-likelihood ratio?SD-LLR?information at the initial stage of decoding by using multi sensing levels,increasing the sensing and transferring latencies.On the other hand,because of high decoding complexity,the SD-LLR information is updated frequently,leading to increased iteration latency.It has become a hot research topic how to study efficient LDPC error correction algorithms.For the decoding iteration latency problem,the noise interference model of flash memory channel is analyzed.Focusing on the application characteristics of program interference errors,PEAL:program interference error aware LDPC decoding is proposed.The numerical correlation characteristics of program interference are transformed into the external SD-LLR information of LDPC decoding.During the decoding process,the external SD-LLR information is integrated into the decoding decision process to improve the dimension of the decoding decision and the accuracy of updating the SD-LLR information,and to reduce the iteration latency of decoding.The simulation results show that compared with the traditional normalized min-sum?NMS?decoding algorithm,when the information length is 2KB and the RBER is115.?10^-3,the LDPC decoding iterations are reduced by 69.37%,and the decoding convergence speed is increased by 2.5times.Focusing on the application characteristics of retention errors,CooECC:a retention error aware cooperative error correction scheme is proposed.By combining the threshold voltage drift characteristics by retention errors with the decoding results of the least significant bit?LSB?page,the initial SD-LLR information of the most significant bit?MSB?page is optimized.The accuracy of the initial SD-LLR information is improved,the decoding iterations and latency of the MSB page are reduced.The decoding latency gap between the MSB and the LSB page is narrowed.The simulation results show that when the information length is 2KB and 4KB,respectively,and the RBER is8.0?10^-3,the decoding latency is reduced by 87%and 84%,respectively,compared with the traditional NMS decoding algorithm.For the sensing and transferring latencies problem,the application optimization method of RBER aware sensing levels in 3D stacked MLC flash memory is proposed.By exploiting the variation of RBER caused by the threshold voltage distribution?TVD?characteristics of 3D floating gate?FG?multi-level cell?MLC?flash,the sensing levels with different numbers and interval lengths are applied dynamically between adjacent TVD.While ensuring the error correction performance of LDPC codes,the number of sensing levels used is reduced,decreasing the sensing and transferring latencies and thus improving the read performance of flash memory.The simulation results show that the average read response latency of low and upper pages is reduced by 25.5%and 20.4%.The error modes aware LDPC soft decoding scheme in 3D stacked triple-level cell?TLC?flash memory is proposed.Firstly,the error mode of 3D charge trap?CT?TLC flash is tested on the real FPGA hardware platform.The data is analyzed to obtain error characteristics and decoding soft decision information of error correction codes.Secondly,the optimized soft decision information is integrated into the variable node information updating and decoding decision processes to improve the accuracy of soft decision information updating and the reliability of decoding decision,reducing the decoding iterations and improving the readperformance of flash memory.The simulation results show that when the information length is 2KB and the RBER is1.8?10^-2,the number of decoding iterations and the system read response latency are reduced by 34.9%and14%,respectively.In summary,the flash error characteristics aware optimization methods of LDPC codes enrich the research theory of error correction codes in flash memory storage systems,and provid a strong guarantee for the further improvement of flash memory capacity.