Research On Acceleration Method Of Floating-point Operation Based On FPGA

With the high technology and socio-economic development. The demand for computerprocessing large magnitude values is growing. Relate to various fields of scientific andsocial. How to quickly achieve high performance scientific computing has become a criticalissue in the current. At present, China in the development of floating-point processor is stillin relatively backward areas of the state. There is a gap compared to the size and gradeabroad.This thesis focuses on the issue of improving operational speed of floating-point. Withmultiplying and adding operations as study object, I have studied and designed the multiplyadd mixed operations of floating-point basing on FPGA. On the basis of analyzing andclearly understanding the multiplying and adding mixed operations of floating point, I haveachieved the research objective by successfully improving the critical techniques ofoperational parts，which functions have been designed by VHDL language and BlochDiagram, besides of simulating this design by using DE2experimental board.In this paper, Depth study structure and design methods of the64bits floating-pointmultiply-add components of the overall. I have mainly designed and completed the criticaltechniques of every process, like Decode、 Multiplier、 Alignment shifter、 LZD、Normalization and rounder. The designs of Multiplier contain symbolic extension、Multiplier produces generation、Selector of one from five、and4:2CSA basing on3:2CSA.Achieve multiplication of the53-bit mantissa. For the integration of basic componentsmultiply adder design and implementation of3:2CSA, compared lookahead adder forfloating-point operations in the acceleration has been improved to provide a basis. Shiftingpart on stage, the paper design161-bit shifter, according to different floating-point index,and analyzes shifter three cases. In addtion, the article analyzes the three LZD algorithm.Designed and implemented LZD predictive coding. Modular coding tree to achieve LZD.Finally, the integrated64-bit floating-point multiply-add components to complete theintegration of the overall structure of multiply-add, multiply-add integration to achieveFPGA emulation. Through simulation to verify the results of the various components, theverification results, the floating point arithmetic in speed has improved.