Research And Design Of A Floating Point Unit Based On RISC-Ⅴ Instruction Set

In recent years,the chip industry has shown a trend of rapid growth.Governments and enterprises worldwide are actively investing resources and funding to strengthen research and development and production in this field.Against this backdrop,a new type of instruction set called RISC-Ⅴ has attracted widespread attention and research from scholars both at home and abroad.RISC-Ⅴ instruction set architecture was proposed by the research team at the University of California,Berkeley in 2010.Compared to the Complex Instruction Set Computing(CISC)instruction set,RISC-Ⅴ instruction set architecture has fewer instructions,more standardized instruction formats,and uniform instruction lengths,thereby reducing the difficulty of chip design.Meanwhile,the open-source feature of RISC-Ⅴ also attracts more and more companies and organizations to join in the development and promotion of RISC-Ⅴ,resulting in the rapid development of its applications in various fields.The increase in application scenarios means that processors need to handle more complex data,and more applications require high-precision floating-point operations,such as simulators,emulators,scientific computing,and graphics processing.Therefore,the floating-point unit,as an important component of the computer,has become one of the important research directions in computer architecture and chip design for its research and optimization.Based on the RISC-Ⅴ floating-point instruction set,this paper presents a floating-point arithmetic unit that meets the IEEE754 single-precision floating-point standard and performs floating-point addition,subtraction,and multiplication.The main contributions of this paper are:(1)the design of a four-stage pipeline architecture for the arithmetic unit based on logical functionality and operation sequence,where each pipeline stage can operate in parallel to enhance the operational efficiency of the arithmetic unit;(2)algorithmic optimization of complex modules involved in the arithmetic process,such as the use of a K-S tree structure in the floating-point adder for mantissa addition,which significantly improves speed compared to traditional serial addition,and the adoption of an improved 4:2CSA-based Wallace Tree structure in the floating-point multiplier to handle the partial products addition;and(3)the use of result bypass design to eliminate redundant calculations in some special cases during the operation,further improving the efficiency of the arithmetic unit and reducing power consumption.After completing the design,the entire data path and arithmetic unit were simulated and synthesized.The results show that the proposed floating-point arithmetic unit can execute RISC-Ⅴ floating-point addition,subtraction,and multiplication instructions.The design of the four-stage pipeline structure enables both the adder and multiplier to meet the clock frequency requirement of 100MHz.The power consumption synthesized under the TSMC 90nm process library is 1mW and 0.7mW for the adder and multiplier,respectively,which is lower than that of the open-source RISC-Ⅴ floating-point arithmetic units on the market.The results of this study provide a new implementation solution for RISC-Ⅴ floating-point arithmetic units that meets national strategic needs.