Design And Verification Of ALU Float-point Arithmetic Unit For DSP Chip

The surge in demand for digital signal processing in the information age has led to the widespread application of DSP(Digital Signal Processor)in various fields.As one of the core components within the DSP chip,the ALU floating-point arithmetic unit directly affects the overall operation speed,circuit area,and power consumption of the DSP.In response to the actual needs of anonymous DSP research and development project,this thesis designs an ALU floating-point arithmetic unit,proposes an automatic generation method for chip verification instruction set,and uses it for simulation verification of all arithmetic units in anonymous DSP.This thesis designs an anonymous DSP chip ALU floating-point arithmetic unit,which is divided into four modules based on instruction function and modular design idea:floating-point addition and subtraction module,floating-point conversion module,floating-point lookup table module,and floating-point other function module;and completes the internal structure design of each module,including designing an improved floating-point dual path structure for the floating-point addition and subtraction module;simultaneously optimizes the execution of corresponding instructions in each module;the ALU floating-point arithmetic unit is implemented using Verilog language encoding.This thesis also proposes an automatic generation method for chip verification instruction sets based on the intermediate form of instruction,which is based on object-oriented thinking.Instruction templates,basic constraints,and additional constraints are defined,and algorithms are designed to achieve multi types automatic generation;coverage evaluation criteria are designed to evaluate the verification instruction set and improve its quality.By constructing a simulation verification platform,this thesis completes the verification of each module and the overall operation component of the designed ALU floating-point arithmetic unit.This thesis uses the Design Compiler tool to analyze the performance of the ALU floating-point arithmetic unit.It is synthesized in an environment with a 40nm process and a clock frequency of 600MHz.The designed unit has a critical path delay of 405ps,a total power consumption of 12.014n W,and a circuit area of 58443.7109μm~2.The comprehensive results indicate that the ALU floating-point arithmetic unit designed in this thesis meets the standard in terms of performance.Finally,the anonymous DSP chip is applied to EEG signal processing system,and the experimental results show that the ALU floating-point arithmetic unit designed in this thesis can meet the real-time processing requirements of relevant floating-point data in EEG signals.