Research And Design Of Transmitter FFE And Receiver CTLE Based On TSMC 0.18μm CMOS Technology

With the development of new generation electronic communication technology,the throughput of data increases,and the higher the data transmission rate is required.The non-ideal characteristics of the transmission channel can lead to signal distortion and affect the integrity of the transmitted signal.In order to improve the quality of the signal,it is common practice to use various equalization techniques.By compensating for the high-frequency loss of the channel,the high-frequency component and the low-frequency component of the signal are balanced,thus eliminating inter-code interference in high-speed serial links and improving the quality of the eye diagram.Firstly,this paper analyzes the influence of non-ideal characteristics in backplane channels on signal transmission.Secondly,two mainstream equalization technologies are introduced.Lastly,the combined structure of a high-speed serial link is analyzed by the ADS simulation platform and the performance of combined equalizers with different structures is compared.Through serial link simulation,the accurate tap coefficient and tap number of feedforward equalizer(FFE)at the transmitting end are obtained.Considering the area,power consumption,and feasibility,the optimized 5-Tap FFE+continuous-time linear equalizer(CTLE)structure is selected as the combined equalizer structure.In this paper,a 10 Gb/s 5-Tap fractional interval feedforward equalizer with a 3T/4symbol period is designed by TSMC 0.18μm CMOS technology.An active delay line realized by a CMOS all-pass stage is used.The delay time of the delay line is 75ps,meeting the requirements of transmission rate of 10 Gb/s.This paper completes the pre simulation,layout design and post simulation of feedforward equalizer.The layout area of the whole equalizer including the pads is 0.086×0.086mm~2.The post-simulation results show that for 10 Gb/s PRBS7 signals passed through fractionally-spaced the feedforward equalizer and 18-inch FR4 backplane,the eye-opening is greater than 0.2 UI,which indicates that the inter symbol interference has been partially eliminated.In this paper,a 10 Gb/s dual loop adaptive CTLE with spectrum balancing is designed by TSMC 0.18μm CMOS.The bandwidth and gain of the linear equalizer are improved by the inductive parallel peaking technique and source degeneration technique.The rate range of adaptive CTLE with spectrum balancing is extended by adjusting the cutoff frequency of the low-frequency and high-frequency of the active hybrid filter.At the same time,DC offset cancellation loop(DCOC)is used to reduce DC offset caused by device mismatch,noise and other factors.The adaptive CTLE with spectrum balancing is completed.The layout area including the pad is 0.11×0.13mm~2.The simulation results show that the 10 Gb/s PRBS7 signals are transmitted through the 18-inch FR4 backplane with a loss of 15.451 d B at the Nyquist frequency,and after equalization by the equalizer,the eye-opening reaches 0.5 UI.