The Research And Design Of Adaptive Redriver For High-Speed Links

With the popularity of mobile internet and the emerging technologies such as cloud computing and big data,the demands for data transmission rate are getting higher and higher in communication systems.Due to the channel attenuation with frequency,crosstalk,reflection and other no-ideal effect,signal integrity in high-speed transmission systems will be deteriorated.In order to improve the communication quality,the equalization technique is frequently adopted in the high-speed system,which can reduce the inter-symbol interference?ISI?by performing high-frequency compensation on the transmission channel.Since the length,material and some other parameters of the transmission channel are different in application,the attenuation of the channel is uncertainty.To avoid under-or over-compensation for the attenuation,a straightforward solution is to employ the adaptive technology.Adaptive equalizer has become the hotspot at home and abroad in recent years,however,the design and implementation of the high-speed adaptive equalizer are facing some difficulty,which need to be optimized and have a good compromise in such parameters as integration complexity,equalization performance,operating speed,and power dissipation.In this work,the architectures of the adaptive redriver used in the high-speed serial links is studied,and based on the USB3.1 backplane system,a 5Gb/s adaptive redriver is designed and verified.In this dissertation,a low offset high speed CMOS differential limiting amplifier was proposed for equalizer system firstly.The techniques include active load inductive peaking and continuous-time active feedback.In order to attenuate the offsets coming from mismatch between devices,an improved offset cancellation technology was implemented,by using 18 pF capacitor in the voltage-current feedback network,the design can provide a high-pass cutoff frequency of 22.8 KHz in typical condition.And Monte Carlo simulation shows that the design has a low offset voltage of 3.73 mV at 1 sigma on the output of limiting amplifier with a mean value of 78.48 uV.Consuming 23.6 mW from 1.8V power supply,the design achieves a 6.96 GHz bandwidth and 24.2 dB gain.Secondly,based on the extensive research and in-depth study of the existing adaptive equalizer,a 5 Gb/s adaptive redriver with a new adaptation architecture is presented here by using 0.13 um CMOS process,which employs both continuous time linear adaptive equalization in the receiver and de-emphasis equalization in the transmitter driver.The designed system mainly consists of equalizer amplifier,limiting amplifier,the adaptation control loop and transmitter driver.To obtain the boosting gain in high frequency,source degeneration structure is adopted in the equalizer amplifier,by using digital control signal to adjust the source degeneration network,the equalizer can achieve as high as 18 dB peaking at 2.5 GHz.The adaptation control loop includes variable gain amplifier?VGA?,low-pass filter?LPF?,all-pass filter?APF?,power detector,error amplifier,high speed comparator and digital finite state machines?FSM?.Under the control of the integrated clock and FSM,the system first enters into the low-frequency gain loop training to adjust the gain of the VGA by comparing the low-frequency energy between the VGA's output and equalizer amplifier's output.In the high-frequency gain loop training,the output of the VGA works as the reference,and the appropriate equalization level can be acquired by comparing the energy between the VGA's output and equalizer's output,which can compensate for the channel loss well.For the design of transmitter driver,constant de-emphasis euqalization level is employed to improve the communication quality.Finally,measurements were performed on the system with a designed PCB trace.During the test,a PCB trace with-3 dB bandwidth of 844 MHz is used as the lossy channel,a signal of 5Gb/s pseudo random binary sequences?PRBSes?of 2²³-1 with BER=10^-12 and 1V_p-p is sent to the chip as the input through the lossy trace,and the output signal measured with an ac couple capacitor of 100 nF in series with 50 ohm load.Test results show that the input eye is almost closed after the transmission through the lossy PCB trace,while after the equalization,the vertical eye opening is improved significantly,higher than 800 mV,and the residual jitter at the output of the equalizer is 46 ps?0.23 UI?,eye-width is 154 ps?0.77 UI?.The eye diagram of the transmitted data is re-shaped by the designed system.For the transmitter equalization,transient results demenstrate that the function is as predicted.The adaptive redriver core occupies an area of 0.3567 mm² and consumes a power consumption of 81.7 mW with 1.8V power supply.And the designed device satisfies the application requirement,in comparison with the existing redriver system,a comparable performance is ahcieved.