Research And Design Of A Low Spur,High Temperature Charge Pump PLL Based On 0.18?m CMOS

The rapid development of integrated circuits has continuously improved people's lives.The increasing demands in social and living conditions have prompted integrated circuits to develop toward high speed,low power consumption and low cost.The application-specific integrated circuit(ASIC)contains many functional modules,such as microprocessors,memories,analog circuits,and digital circuits.These modules need to work under certain timing conditions in order to implement various system functions.So there comes a need for a clock signal source.Clock source based on phase-locked loop(PLL)technology has been widely developed and used in recent years and has become one of the main choices of clock generation sources in ASIC.Therefore,it is of great significance to study the PLL which can be applied to ASIC circuits.This paper has discussed the PLL technology and basic principles of the PLL system,analyzed the locked state,system classification and typical structures.Next,the key modules of charge pump phase-locked loop(CPPLL)are analyzed in detail.This part of the work provides a theoretical basis for the subsequent design of the PLL system.Next work is the design and simulation of the entire PLL system under Cadence,which mainly includes the design of a fully differential ring voltage controlled oscillator,based on an inverter without tail current source,adding a bypass to form a delay cell.The voltage controlled oscillator has the characteristics of simple structure,rail-to-rail output,and good phase noise performance.Meanwhile,the structure is improved for high-frequency applications,and the improved circuit can reach a output frequency up to 1.23GHz with good phase noise performance.A charge pump structure that improves the non-ideal effects of switching is adopted,and it provides a well-matched output current.Then use Matlab/Simulink to build the system model for verifying the stability.Simulate the transient performance,spurious performance,and temperature performance of the PLL in the Cadence/Spectre simulator.Complete the layout of the entire circuit and carry out post-simulation verification,give the testing plan of key modules and the testing ideas of the entire system.The PLL,based on sensor applications,finally realized in this paper has an output range of 7.6?8.6MHz,lock time less than 10?s,and the jitter less than 10ps.When the reference clock is 8MHz,the circuit can work correctly at the temperature range of 2 5??175? with the reference spur about-190dBc.The simulation results show that this PLL can achieve fast locking time and track the input signal in real time.It meets the design requirements,and has been delivered to the factory for tape-out.