| The frequency synthesizer is an important building block in most communication systems, whose performance is greatly affected by the phase variation of the frequency synthesizer output, including the random phase noise and spur-associated variation.; This thesis firstly reviews the characteristics of frequency synthesizers and a number of frequency synthesis technologies to date. Then noise performance of two typical frequency synthesis technologies, the phase-locked loop (PLL) based one and the delay-locked loop (DLL) based one, is analyzed theoretically in detail. The circuit components critical for the synthesizer performance are also discussed respectively. To suppress the spurious power level in the synthesizer output, a new architecture of a DLL-based frequency synthesizer is proposed, in which a novel phase comparison circuit, including a charge pump phase comparator and a lock detector, is employed. Compared to the conventional non-dead zone phase comparator, the novel charge pump phase comparator provides a high phase resolution and a small timing offset. With the lock detector, the phase comparison circuit can operate in as extended phase range. This DLL-based frequency synthesizer is thus expected to exhibit low spur content, low phase noise at its output and operate in a large frequency range. This frequency synthesizer is implemented in 0.18 mum CMOS process. Its input frequency range is from 110MHz to 230MHz and its output frequency is nine times the input. The measured output spur power is -46.17dBc and the phase noise is -107.17dBc/Hz at 10kHz offset with the reference frequency of 173MHz from an RF signal generator, which is better than all other reported results to date and verifies the successful implementation of the design. |
