Research On The Structure Of FinFET Ternary SRAM

Over the past few decades,the number of transistors integrated on a chip and performance obtained the very big enhancement,however,with the reduction of the characteristic size of microelectronic devices,the limit of some physical problems such as the short channel effects has been faced with.Reducing power consumption and improving the performance/power ratio will replace increasing integration level(reducing feature size),as the driving force for the development of integrated circuits and integrated micro-nano systems in the future.The current popular new process technology,FinFET structure,mainly used in memory,can signally reduce the impact of short channel effect.Memory of static random access memory(SRAM),with the advantages of high speed and ease of use,is widely used in system on chip(SoC),determining the performance of the chip to a large extent.There are some problems on traditional 6T SRAM cell,such as read operation damage,a little unreliable read/write stability and large leakage current.This paper first analyzes the necessity of scaling down the traditional transistor,the challenges encountered and the solutions to them,so as to introduce a new device structure called FinFET.Secondly,the FinFET structure and the simulation model are introduced,and several main binary SRAM cell structures have been analyzed and compared,the performance parameters of the existing ternary SRAM cell structure are simulated and analyzed.Then the advantages and disadvantages of various SRAM cell structures are obtained,and a new ternary SRAM cell circuit based on FinFET is proposed according to the obtained rules.In this paper,the ternary inverter is designed by using the characteristic of FinFET,and the data storage is realized by cross-coupling method.Read-write isolation technology and transmission gate technology are introduced into the circuit to avoid read-write conflicts and improve write stability.Through the HSPICE simulation of the newly designed ternary SRAM cell,it is shown that the proposed design structure has some advantages in reducing leakage current and power consumption,and in improving the read-write stability of the circuit.