The Research Of High Voltage SJ LDMOS Structure Based On Charge Balance

Lateral power LDMOS(Lateral Double diffused Metal Oxide Semiconductor Field Effect Transistor)plays an increasingly important role in the power integrated circuit PIC(Power Integrated Circuit)and the high voltage integrated circuit HVIC(High Voltage Integrated Circuit),because of its high input impedance,fast speed,high integration,low power consumption and so on.With the gradual development and maturity of PIC technology,LDMOS has been widely used in the fields of consumer electronics,automotive electronics,home appliances,and communication electronics.However,there is a serious contradiction between the BY(Breakdown Voltage)and the iRon,sp(Specific On Resistance)with the development of LDMOS,that is say,Ron,sp?BV2.5.The increase in BV and the decrease in Ron,sp are limited by the doping concentration and length of the drift region.The emergence of SJ(Superiunction)technology and its introduction into lateral devices has broken the "silicon limit",that is,the Ron,sp?BV2.5 is transformed into Ron,sp?BV1.32 and then becomes Ron,sp?BV1.03,which makes the SJ power device become a hot topic of research.But,the lateral SJ LDMOS cannot be completely deplete due to the potential difference between the electrodes,resulting in a sharp drop in the BV of the lateral SJ LDMOS.This phenomenon is known as the SAD(Substrate Assisted Depletion Effect),which reduces the performance of the lateral SJ LDMOS and hinders the development of lateral SJ LDMOS.Based on the charge balance theory,two type novel SJ LDMOS structures are proposed by optimizing the CCL(Charge Compensation Layer).The performance of the SJ LDMOS is optimized through a combination of theoretical analysis and simulation.(1)The SJ LDMOS structure with a PLK(Partial Low K Layer)is proposed.The main feature of the PLK SJ LDMOS is that it has a partial low K dielectric layer.The segmented linear doping technique is applied in the drift region.The doping concentration distribution of the drift region is optimized according to the position of partial low K dielectric layer,thereby shielding the SAD of the PLK SJ LDMOS and ensuring the charge balance of the SJ layer.Since partial low K dielectric layer is introduced below the drain of the PLK SJ LDMOS,the vertical buried electric field of the PLK SJ LDMOS is increased.Finally,the vertical BV of the PLK SJ LDMOS is improved.With the drift region length is 45?m,the BV and FOM(Figure of Merit)of the PLK SJ LDMoS are 799V and 6.2MW·cm-2,respectively.Then,according to the structural characteristics of PLK SJ LDMOS,the corresponding process preparation scheme and runway layout are given.(2)The SJ LDMOS structure with GCCL(Gradient Charge Compensation Layer)is proposed.The main feature of the GCCL SJ LDMOS is the gradient eharge compensation layer.The shape of the GCCL between the SJ layer and the substrate is triangular.By optimizing the shape of the charge compensation layer to optimize the compensation charge distribution in the charge compensation layer,the SAD of the SJ LDMOS is eliminated,thereby ensuring the charge balance of the SJ layer in the SJ LDMOS.With the drift region length is 21pun,the BV and FOM of the GCCL SJ LDMOS are 409V and 9.5MW·cm-2,respectively.Next,the process preparation scheme and the runway layout are given for the structural characteristics of the GCCL SJ LDMOS.