Mos Structure Based On Separation Of Charge Stored In The Storage Effect And Mechanism

With development of semiconductor technology and downscaling of the memory device size, conventional poly-silicon floating gate flash memories are facing severe challenges. Embedded nonvolatile flash memory devices based on discrete charge storages have recently drawn great attention as a promising replacement of the conventional poly-silicon floating gate structure due to improved retention characteristics in the case of a thinner tunneling layer, and faster program/erase (P/E) speed under lower operating voltages. Based on discrete dielectric traps and metal nanocrystals as charge storage media, in combination with atomic-layer-deposited high permittivity (k) dielectrics and energy band engineering of tunnel layer, this thesis presents memory effects of the corresponding metal-oxide-silicon (MOS) structures, and the involved physical mechanisms are also discussed. The details include the following sections:Using high temperature oxidized SiO₂ as tunnel layer, atomic layer deposited (ALD) HfO₂ as charge trapping layer, ALD Al₂O₃ as blocking layer, charge trapping characteristics of the metal-insulator-silicon (MIS) capacitors with SiO₂/HfO₂/Al₂O₃ stacked dielectrics have been investigated. A capacitance-voltage (C-V) hysteresis memory window as large as 7.3V is achieved for the gate voltage sweeping of +/- 12V, and a flat-band voltage shift of +1.5V is observed in terms of programming under 5 V and 1ms. Furthermore, the time- and voltage-dependent charge trapping characteristics are also investigated, including quantity of injected charges, charge injection rate and retention characteristic of trapped charges. These are discussed according to the mechanisms of charge injection and leakage.Using e-beam evaporation and rapid thermal annealing (RTA) techniques, growth of Pt nanocrystals on ALD Al₂O₃ film have been studied. The results show that Pt nanocrystals with a high density of 2.5×10¹¹ cm^-2 and a mean diameter of 8 nm have been achieved after annealing at 700℃for 30 s. Further, MIS capacitors with ALD Al₂O₃ as tunnel layer, Pt nanocrystals as charge trapping layer, ALD HfO₂ as blocking layer have been fabricated and tested. A C-V hysteresis memory window of 2 V is achieved for the gate voltage sweeping from -3 V to +8 V, and a flat-band voltage shift of +2.4 V is observed in terms of programming under 10 V and 900 ms.Using magnetic sputtering and RTA techniques, growth of Co nanocrystals on ALD Al₂O₃ film have been studied. Uniform and compact Co nanocrystals are formed after annealing at 500℃for 15 s. Further, MIS capacitors with ALD Al₂O₃/HfO₂/Al₂O₃ (A\H\A) as tunnel barrier, Co nanocrystals as charge trapping layer, ALD HfO₂ as blocking layer has been fabrication and investigated. Compared to the identically thick Al₂O₃ tunnel barrier, the A\H\A tunnel barrier can increase significantly the C-V hysteresis window, indicating an increase by 9 V for +/-12 V sweep range. This is attributed to a marked decrease in the energy barrier of charge injections for the A\H\A tunnel barrier, and it helps to increase the charge injection rate. Therefore, the Co-nanocrystal memory capacitor with the A\H\A tunnel barrier exhibits a perfect memory window as large as 4.1 V for 100μs program/erase at a low voltage of +/-7 V, which is associated with fast charge injection rates, i.e., ².4×10¹⁶ cm^-2s^-1 for electrons and 1.9×10¹⁶ cm^-2s^-1 for holes.