Research On Key Process Of Tunneling Field Effect Transistor Devices

With the development of the integrated circuit field,the integration of the chip is increasing while the size of the MOSFET device is also shrinking.Today,the problem of increased power consumption due to device size reduction becomes more and more important.For traditional MOSFET devices,the trade-off between power consumption and performance has become an increasingly difficult contradiction.At room temperature,due to the limita-tion of carrier thermal emission mechanism,the subthreshold swing of MOSFET can not be lower than 60 mV/dec.As a new type of low power device,tunneling field effect transistor(TFET)'s working mechanism is the band-to-band tunneling of carriers.The subthreshold swing of the device can exceed the limit of 60 mV/dec,which can greatly reduce the static power consumption of the device,and the TFET has low off-state current and high processing compatibility.That's why TFET is considered to be one of the most promising competitors to replace MOSFETs.However,TFET devices still have some problems of their own.For example,the on-state current of TFET is generally small and the average subthreshold swing of the device does not reach the ideal value.At present,many domestic and foreign experts and scholars are solving these problems of TFETs by studying new structures and applying new materials.Among them,there are few domestic experiments on TFET devices.In order to explore the solution to these problems,this paper optimizes the structure of TFET devices and explores the factors affecting the performance of TFET devices through fabrication process.The specific research contents are as follows:1.This paper deeply studies the mechanism of TFET devices,and optimizes the structure of TFET devices by analyzing the factors affecting the performance of TFETs.The gate-source overlap is achieved by extending the gate into the source region,thereby increasing the tunneling area of the tunneling junction and the tunneling electric field at the source-channel interface.Simulation results show that the structural optimization can improve the performance of TFET devices.2.This experiment completed the fabrication process of TFET devices,and made a prelimi-nary exploration of the TFET experimental process.The main processes are ion implantation,thin film growth,wet etching and rapid thermal annealing.3.This paper analyzes the ohmic contact,C-V characteristics and interface traps of the device in detail through electrical testing.The difference of contact resistivity caused by ion implantation in the source and drain regions,the influence of annealing on ohmic contact and the process variation of each region on the chip are analyzed by simulation.The trap charge of the gate dielectric-semiconductor interface was characterized by analyzing the hysteresis of the C-V positive and negative sweep and the abnormal”protrusion”of the dispersion characteristics.4.The gate leakage current and transfer characteristics of the device are analyzed,wherein the gate leakage current is small,below the order of nA.The current switching ratio is 10~2approximately,the minimum subthreshold swing of approximately 108 mV/dec,and an aver-age subthreshold swing of more than 230 mV/dec.The device characteristics are not ideally because of the large contact resistance and the exist of interface trap charge,and the gate leakage is sharply increased in the second test one month after the separation,and the C-V characteristics are completely lost,which proves that the quality of the gate dielectric de-grades obviously with time,it eventually leads to device failure.5.A summary of the experiment.The experimental results show that the device exhibits cer-tain gate control capability.Although the device characteristics are not as good as expected,this experiment has explored and tried for the later research,and found some optimization schemes,for example:in the future,more parameter comparison groups and single step pro-cess tests should be added to optimize the experimental conditions,and the wafer should be passivated to ensure the quality of the gate dielectric film and prevent the degradation of the oxide layer to cause device failure.