Design And Implementation Of I~2C And SSPI Bus Configuration System Based On FPGA

FPGA(Field Programmable Gate Array)is a field programmable gate array.This integrated circuit chip can provide users with a large amount of logic resources.Users can define their functions by changing the configuration information of the chip according to their own needs,thus achieving different application functions.Therefore,system configuration is a very important part of the FPGA chip.An FPGA chip can work normally after it is successfully configured by configuration systems.Almost all of the widely used chips have configuration system inside,but they are monopolized by Xilinx and Altera.Therefore,designing domestic FPGA configuration chips with independent intellectual property rights becomes more and more important.The topic of this paper comes from the sub-project of the design project of28-nm Sealion 25k FPGA chip of Xi'an Intelligence Silicon Technology,Inc.It focuses on the design of a configuration system of I~2C,SSPI and JTAG bus interface based on FPGA.The main work of this paper includes the following aspects:First,this paper introduces the development of FPGA configuration chips at home and abroad,and discusses the significance of designing domestic FPGA configuration chips.The overall design framework of the I~2C,SSPI and JTAG bus interface configuration system based on FPGA is determined according to the concept and functional indicators of the chip configuration system.Any FPGA configuration system consists of configuration control module,configuration read-write module,additional function module,and configuration data protocol that matches the structure.The configuration control module is mainly implemented by finite state machine and control register.The configuration read-write module is implemented by serial bus interface.The additional function modules can realize software error detection,decrypt encrypted data,chip information protection and other functions.The configuration data protocol is implemented by its own set of instructions.Secondly,according to the overall framework of the configuration system,this paper first defines the top-level functional blocks with the top-down design method,and then analyzes the necessary sub-modules that constitute the top-level module,including the control module,data synchronization module,configuration read-write module and additional function modules.At the same time,each module is designed and simulated by using Verilog HDL language.The control module is mainly implemented by bse state machine,fsm state machine,refresh state machine,wake up state machine and control register;data synchronization is realized by asynchronous FIFO;configuration read-write module is realized by interfaces such as I~2C,SSPI and JTAG.The design of SSPI bus interface is the innovation of this paper.It is different from the traditional serial bus that can only achieve1-bit input.In this paper,the SSPI interface can realize 2-bit and 4-bit input without adding extra pins.Additional function modules include SED checking,AES decryption and EFUSE protection module.EFUSE protection is the innovation of this paper.Unlike the traditional EFUSE protection,the EFUSE module in this design includes three modes:norm,sudo and safe.It can not only realize the functions of chip protection information,but also store important data.Finally,the function simulation platform for the configuration system is designed and the function simulation of each module is carried out.The simulation results show that the modules of the configuration system realize all expected logic functions and verify the correctness of the logic functions of the designed system.The layout of the whole configuration system is obtained by integrating Verilog HDL code and timing optimization according to the process of the design of the FPGA.The layout is given to the manufacturer for streaming.The successful test chip of the streaming chip is debugged on board,which verifies that the function of the design is correct and the FPGA chip can be successfully configured.In summary,the configuration system designed in this paper can successfully configure data for FPGA chips,and each of its module meets the design requirements,as well as its timing meets the design targets.Thus the configuration system achieves the expected goals of the paper.