Research And Design Of FPGA Configuration Data Check And SEU Effect Detect

In order to meet the needs of the user's high-end applications, high-performance FPGA must be able to support the function of configuration data check and SEU (Single Event Upset) effect detect. Against the demand, the paper conducted a study of FPGA configuration data check and SEU effect detect. According to configuration data and read-back data format, designed the circuits of configuration data check and SEU effect detect. Using the CRC (Cyclic Redundancy Check) algorithm check the data.First, function simulation using ModelSim SE6.0, and then using smic18_tt CMOS process and Synopsys company's Design Compiler tool synthesize, get the circuits and do simulation after synthesizing. The experimental result indicates that in meeting the conditions of timing and reasonable occupied area, the circuits can realize the function of configuration date check and SEU effect detect, and operating frequency up to 166MHz, meeting the design requirements.