Design And Research Of High - Speed FPGA Configuration Structure

FPGA is now widely applied in the aerospace and other complex electromagnetic and strong radiation environment. It is facing the threat of various radiation effects preduced by high energy cosmic rays and charged particles, which are most sensitive to SEU. How to improve the capacity of anti-SEU has become the important research direction for FPGA. Anti-SEU design require fast detection speed and error correction efficiency and this make it necessary that FPGA configuration circuit can have quick download and read-back speed. Moreover, with the size increasing of FPGA, the configuration bitstream increases rapidly and this will greatly reduce the efficiency of the system design. Therefore, how to reduce the download and read-back time has become an important research topic for FPGA.Based on above, this paper designs a high-speed FPGA configuration circuit. The design has been used in FDP3P13FPGA chip which is designed independently by Fudan University using a0.18um standard CMOS6layer metal technology. This configuration structure has faster download and read-back speed on the unit bitsream word; support four configuration modes such as master/slave serial, slave parallel, JTAG; design SEU detection circuit which can work continuously for read-back CRC. Test results indicate that:FDP3PI3improves the download time of unit word by23.67%based on209%increasing for each frame; FDP3P13can complete the whole chip configuration in38.56ms.In addition, this paper also designs the AMBA high-speed configuration bus for FDP3P13. Simulation indicates that FDP3P13can be downloaded and read-backed rightly throuth AMBA bus. The maximum frequency can be up to160MHZ.