Data Preloading And Data Placement For LTE Performance Improving

With the increasing design volume of So C,the speed of simulation becomes one of the shortcomings that restrict the verification progress.Due to the limitation of simulation speed,some test results of big data volume cannot be quickly presented in RTL level simulation.However,although the industry's mainstream FPGAs and dedicated simulators can be used to solve the problem of slow RTL simulation speed,there is no way to observe hardware signals and internal logic transparently like RTL-level simulation,and it is impossible to set breakpoints at any time.Debugging hardware,so RTL-level simulation is still not a substitute,so how to improve the efficiency of RTL simulation is particularly critical.In addition,in a So C chip,the area occupied by the memory is greater than 60%,and an increase in the area necessarily causes the memory to be more susceptible to radiation interference and cause errors.Therefore,suppressing the error of the memory can greatly enhance the anti-interference ability of the system to the outside world.On the other hand,with the development of IC design process,the density of memory on the chip is increasing,so that the types of defects that may occur are more and more,and the amount of data verified becomes more huge,which greatly increases the number of To verify costs,the original verification process has been difficult to address these new challenges.From the perspective of data loading mode,front door access refers to physical timing access through the bus.This access needs to go through the bus protocol,so access takes time,and the front door access can be ended when the bus access ends,compared to the front door.Access,backdoor access can be directly read and hardware modified by associating hardware memory signal paths,without access time and without hardware timing control,but this approach may cause timing conflicts,but in turn,this can be done Through the bus protocol,the bus error is effectively captured,and then the path of the bus access is verified to be correct,such as whether the design and verification are synchronized in real time.In addition,the premise of using backdoor access is that the design to be tested has been fully verified on the basis of front door access.In order to solve the problem of time-consuming access to the front door,this paper takes the pre-silicon verification of LTE module as the background,and starts with the data loading method,studies the memory characteristics in the LTE module,and the error correction principle and decoding method of error correction coding.The fast data access speed effectively improves the RTL simulation speed of LTE module test cases.Based on the script development based on Perl language,the RTL simulation process of backdoor data loading,including the preparation of Makefile,and the details of script development are elaborated.The backdoor data loading based on the LTE module is implemented,and the possible timing conflicts are solved.Since the backdoor data loading is directly read and the hardware is modified,the ECC check bit needs to be manually added.Therefore,the reliability analysis of the reinforcement scheme is required.Observe the output data and the coverage analysis of all test scenarios by adding a single bit error to the input data and compare it with the system time consumed by the front gate data loading.The conclusion is that the backdoor data loading is applicable to all test scenarios,and the RTL simulation time consumed is about 40% of the front door data loading time.The feasibility of the scheme is verified and applied to the actual project.