Front-end Design Of Passive Chip For Resistive High-precision Sensor Based On NFC

At present,with the coming of the 5G era and the vigorous development of the Internet of things,NFC technology has been developing rapidly in various fields.One of the applications is to combine NFC technology and sensor technology to realize monitoring of some common physical quantities.Resistive sensor is one of these sensors.This paper designs a readout circuit for resistive sensor interface based on NFC.Aiming at the cost and power consumption of NFC circuit,the design of 13.56 MHz passive tag chip analog front-end circuit and resistive sensor readout circuit in line with ISO14443 protocol standard has been completed.In order to provide reference voltage for the tag chip,a low power consumption,low temperature drift reference circuit is designed.The circuit consists of a current reference circuit,a bipolar transistor and proportional-to-absolute-temperature(PTAT)voltage generators.The proposed circuits avoid the use of resistors and contain only MOSFETs and one bipolar transistor.The simulated result obtained in the SMIC 0.18?m process demonstrates that the BGR circuit could generate a reference voltage of 0.5 V.The power dissipation of the BGR circuits is 120 n W.The temperature coefficient is 72ppm/?.In order to provide a continuous and stable clock for the digital baseband of the chip,a clock circuit based on PLL is adopted.The circuit can generate continuous 13.56 MHz clock signals,and the clock deviation is 115 KHz.The power consumption is 5.6?W.In order to achieve high efficiency rectification of input RF signals,the NMOS and PMOS gate cross coupled rectifier circuits with threshold compensation are adopted.When the input frequency and amplitude are 13.56 MHz and 3 Vpk-pk,respectively,the output voltage is 2.47 V,the voltage ripple is 4.7m V,the load is 100K?,and the conversion efficiency is 85.1%.In order to get a stable power supply voltage,a LDO with super source follower structure is adopted.A power on reset circuit and a demodulation circuit as well as a modulation circuit are designed to complete the design of the NFC analog front-end circuit.Finally,a read-out circuit for resistive sensors is designed,converting resistance to frequency which can be processed by digital circuit.In this topology,a switched-capacitor circuit is controlled by an internal voltage-controlled oscillator(VCO),and the equivalent resistance of this switched-capacitor is matched to an off-chip resistor of the sensor using an ultra-low power amplifier.This design yields a temperature-compensated frequency from the internal VCO.The approach eliminates the traditional comparator from the oscillation loop;this comparator typically consumes a significant portion of the total oscillator power and limits temperature stability in conventional RC.Simulation results show that the variation of oscillation frequency is only 1.2‰ from-40? to 80?,and the minimum capacitance could be detected is 50? when resistance values are in the range from 1M? to 1.2M?.The entire read-out circuit operates at 200 k Hz oscillation frequency with 20.1?W power consumption.All the circuits mentioned above are designed using SMIC 0.18?m process and simulated by Cadence.The simulation results prove the design meet the demand of expect.