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Research On Key Techniques Of CMOS Analog Front-End For Power Line Communication

Posted on:2016-11-29Degree:MasterType:Thesis
Country:ChinaCandidate:P Z PanFull Text:PDF
GTID:2348330488472982Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Given its ability to transfer data over the same lines used to carry power, Power Line Communication?PLC? technology offers a cost-effective communication media for a wide range of applications, which is also suitable for baseband coaxial and phoneline wireline media. By eliminating the need to install additional wires to interconnect devices, PLC substantially reduces system cost and increases reliability while enabling efficient communications in environments that might otherwise be too expensive to network. However, power lines are inherently noisy and require a robust architecture to ensure data reliability. As a vital interface module in PLC systems, the transceiver has been attracting more and more attention with the development of CMOS integrated circuits.Low Noise Amplifier?LNA? is usually the first stage of the PLC Analog Front-End transceiver. A variable gain LNA based on a fully balanced differential difference amplifier is proposed in this dissertation, with the addition of a resistive attenuator. Simulation results based on a SMIC 0.18-?m CMOS process show that a gain range of 12 dB and a 3-dB bandwidth of more than 100 MHz are achieved. The P1 dB and IIP3 at the maximum gain are 2.91 dBm and 12.91 dBm, respectively, and the input referred noise is 2.297 nV/Hz1/2 @20MHz. It also reaches a steady common-mode output of the first stage in a wide common-mode input range from 0V to 3.3V and the average power consumption is 43 mW.Also, as an indispensable module of the transceiver, the central part of the Automatic Gain Control?AGC? system is Variable Gain Amplifier?VGA?. Adopting the binary-weighted switching and reconfiguration techniques, a new Programmable Gain Amplifier?PGA? version is proposed that offers a precise and process/temperature-insensitive gain and achieves a double dB-linear range with a small gain error. Implemented in a SMIC 0.18-?m CMOS process, from the measurements, the proposed PGA shows a dB-linear gain range of 42 dB?- 21 to 21 dB? with a gain error of less than ± 0.54 dB, a 3-dB bandwidth of 60 MHz at the maximum gain, a noise figure of less than 15 dB at a 21-dB gain, P1 dB and IIP3 of-9.2 to 0 dBm and-5 to 17.4 dBm, respectively, and small gain errors of less than 0.85 dB were measured over a temperature range of 0 °C to 100 °C, while consuming an average current of 2.1mA from a 3.3-V supply.
Keywords/Search Tags:Power Line Communication, Analog Front-End, Low Noise Amplifier, Programmable Gain Amplifier
PDF Full Text Request
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