Design And Implementation Of The Pipeline ADC For Silicon Pixel Chip Readout Circuit

CEE is the abbreviation of CSR External-target Experiment.It is a large-scale instrument and equipment jointly participated by many domestic universities and research institutes.After the development is completed,it will be my country's first GeV energy zone,self-developed large-scale nuclear physics experimental device based on HIRFL-CSR,a large domestic nuclear physics scientific device.The Silicon Pixel Topmetal-CEE chip is a beam front-end detection used in CEE projects.It works at the forefront of the particle incident beam and is used to measure the position and time information of the incident beam,and providing high-precision initial vertices for other track detectors when reconstructing the track of the final particle.In order to ensure that the output analog amplitude information of the Topmetal-CEE chip can be quantified and read out quickly and accurately,a high-speed and high-precision analog-to-digital converter is essential.Based on the goal,this paper design a 13bit 20MS/s pipeline ADC based on the 130nm CMOS commercial standard process.It will be an important part of the Topmetal-CEE chip readout circuit in the CEE project,and doing high-precision sampling of the analog output of the entire system.The main work and design difficulties are as follows:1?This design adopts the SHA-less pipelined ADC structure,which greatly reduces the system's power consumption while meeting the system's requirements for speed and accuracy.At the same time,it also reduces the complexity of the pipelined ADC circuit and reduces The influence of the noise of the sample-and-hold circuit on the overall pipeline ADC signal-to-noise ratio.2?A detailed theoretical analysis and manual calculation of the error source of the pipelined ADC are carried out.On this basis,a high-level behavioral simulation of the pipelined ADC is carried out,that is,the Verilog-A hardware language and the ideal device in the Cadence default library are used to build.The macro model not only verifies the feasibility of the circuit structure,but also quantifies the signal noise that each module can tolerate on the transmission line.3?Designed a high-gain,high-bandwidth,fully-differential folded cascode amplifier,which embeds gain-boosting technology.The auxiliary operational amplifier and the main operational amplifier use continuous-time common-mode feedback and switched capacitor common-mode feedback circuits,respectively.At the foot of each process,it meets the requirements of the pipelines.After simulation Verification:the power supply is 3.3V,input dynamic range is 1.15V?2.15V,Gain is up to 96.4dB,Unity Gain Bandwidth is up to 1.38GHz,Closed-loop phase margin of about 60°,Output common mode under each process foot are kept at about 1.65V,and the total power consumption is about 0.014mW.4?A dynamic comparator with a large latch structure is designed.It works under f1,f2,and k2 three-phase clocks,where k2 and f2 are in phase,and k2 is closed earlier than f2 to establish a zero-setting state to reduce the influence of the offset voltage and kickback noise of the comparator on the overall performance of the pipeline ADC.After simulation verification:The power supply is 3.3V,and the comparator can complete the comparison within 9ns at each process angle.the offset voltage is floating within 16mv,and the power consumption of the comparator It is about 104?W.5?A dual-phase non-overlapping clock generation circuit is designed.After simulation verification:the working voltage is 3.3V,the clock frequency is 20MHz,the dual-phase non-overlapping time is about 1ns,and there is almost no clock jitter;Digital tools are used to design delay alignment and digital The calibration circuit turns complex timing requirements into controllable and variable steps,and also saves design cycles.At present,the design content based on this project has been completed,the chip area is about 0.72mm2,and the post-simulation results show:under typical process corners,power supply is 3.3V,system sampling frequency is 20MHz,single-ended input dynamic range is ±1V,SNR is about 65.1 dB,SFDR is about 74.4dB,SNDR is about 64.9dB,THD is about 78.3dB,ENOB is 10.48 bits,and the total system power consumption is about 79mW,which basically meets the needs of the project.In addition,this design has been taped out with the Topmetal-CEE chip in the CEE project,and subsequent chip testing and further research will be arranged.