Research And Implementation Of TS Over IP System Based On FPGA

Under the background of triple play,the networking of digital TV has become an inevitable trend.In order to reduce the cost of digital TV system equipment and enhance the extendibility of the system,the traditional digital TV interface(ASI)has been unable to meet the demand of the market.Therefore,it is urgent to transfer the ASI interface to the IP interface equipment to carry the information transmission between the digital TV network and the Internet.This thesis will use the FPGA to design and implement the TS over IP system by converting the format of the MPEG-2 TS stream and intermediate processing to complete the conversion from the ASI interface to the IP interface.The main work includes:(1)This thesis will use the ZYNQ-7020 of Xilinx company and the physical layer network chip 88E1111 to construct the hardware platform of the system,and use the Verilog hardware description language to complete the system function design,including encapsulating the MPEG-2 TS stream of the ASI interface into an IP packet format,TS stream multiplexing,the bit rate smooth and PCR correction.Thus,the design and implementation of the TS over IP digital TV front end system is completed.(2)This system supports the receiving and sending of 256 channel TS streams.In order to facilitate FPGA internal processing,it is necessary to reuse the 256 channel TS flow inside the system.The PID byte in the TS stream is the unique identification of the program information,and the multiplexing operation causes the PID conflict.In order to solve this problem,the concept of custom Baotou is proposed in this thesis,which is adding custom bytes on the basis of the standard TS package structure.By simulation of the system function,we can use the Stream_ID bytes in custom to complete the PID mapping and redistribution.(3)In order to solve the problem of packet loss caused by the overflow of the buffer,the system has proposed an improved ARSBO algorithm based on the dynamic adjustment of the buffer level,based on the research of the rate smoothing algorithm and the advantages and disadvantages of the SRS algorithm and the ARSBO algorithm.Experimental results show that the improved rate smoothing algorithm improves the smoothness and occupies less FPGA resources.(4)The program reference clock PCR carried in the transmission stream TS is the key to the synchronization of codec in the digital TV system,and this system can not guarantee the constant delay in the processing of the TS stream.Thus,the PCR value in the TS flow can not correctly reflect the time relationship between the TS packets and cause the synchronization error of the decoder.In order to ensure the synchronization of encoding and decoding,the system corrects the PCR to meet the requirements of MPEG-2 standard for TS flow PCR jitter and accuracy.The traditional PCR correction algorithm mainly aims at the standard ASI interface signal.In order to correct the TS stream from the IP interface,an improved PCR correction algorithm is proposed.The algorithm compares the time accumulation between the PCR packets and the PCR value,thus completing the correction of the PCR.