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A High Speed Serial Communication Receiver For Duobinary Signaling

Posted on:2019-01-13Degree:MasterType:Thesis
Country:ChinaCandidate:M S ZhangFull Text:PDF
GTID:2428330596960518Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
With the advent of big data and 5G communications era,it seem that the requirement of more efficient and more safer data transmission is increasing day by day.Advanced semiconductor processes and circuit structures can significantly improve the signal processing rate of the SerDes transceiver,while the limited bandwidth channel between high-speed serial communication links becomes the bottleneck restricting the data transmission rate.Therefore,multi-level signaling schemes have received much attention of late because they can reduce channel bandwidth requirement compared to the NRZ scheme.Among them,duo-binary(DB)signaling has extensive research value because it can reduce the bandwidth requirements at a relatively low cost of signal-to-noise ratio(SNR).This thesis compares the characteristics of high-speed serial communication using NRZ,PAM4 and DB signaling by ADS,and focuses on analyzing the superiority of multi-level signaling.On the basis of that,a high speed serial communication receiver using duo-binary signaling is completed by 130nm SiGe BiCMOS technology,including continuous time linear equalizer(CTLE),level-shifting limiting amplifier(LSLA),and XOR gate used for decoding.The capacitance degradation technology is used in CTLE circuit to achieve high frequency filtering characteristics to eliminate inter symbol interference(ISI)in received DB signals.The level-shifting(LS)stage is used in LSLA block to shift the middle voltage of the upper eye-pattern(or lower eye-pattern)up(or down)to zero level,and the second LS stage is used to avoid the distortion of the data width after amplification.Finally,the XOR circuit is used to decode the DB signaling to the original NRZ signal.The layout design and post simulation of the receiver have been completed in this thesis.The chip area including I/O pads occupies 0.716mm×0.489mm=0.350mm~2,and the power consumption is about 280mW under 2.5V power supply.Post simulation results show that the proposed high-speed serial transmission receiver for duo-binary signaling can equalize the received 20Gb/s DB signal with severe inter symbol interference(ISI)to the duo-binary signal with an 0.7UI eye opening.And eventually the equalized DB signaling can be converted to an NRZ signal with 0.6 UI eye opening...
Keywords/Search Tags:duo-binary singaling, equalizer, receiver, level-shifting limiting amplifier(LSLA)
PDF Full Text Request
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