Filtering Technology Of Programmable RF Transceiver

With the progress of chip process and circuit design technology,the performance of CMOS transistor switch is improved,no inductance signal path is realized,and digital circuit processing ability is enhanced,which makes the programmable RF transceiver chip possible.In order to meet the requirements of various communication protocols,the maximum tuning bandwidth index of filter groups should be more than 20 MHz,the bandwidth tuning range should be more than 100 times,and the filter group should has the ability of gain regulation.In the absence of high performance filter auxiliary,the on-chip filter group needs to have 80 dB of out-of-band signal suppression in the range of tunable channel,design and implementation is very difficult.This paper focuses on the filtering technology in the programmable RF transceiver,which includes:(1)Starting from the design of the system and architecture of the programmable transceiver,this paper analyzes the requirements of the index of the filter at all levels,and gives the basic design index of filters;(2)The basic principle of simulating active-RC low-pass filter is studied,the influence of the non-ideal amplifier of the analog baseband filter is analyzed in detail,and the cascade design method of analog filter is improved to applied to the limited conditions of bandwidth and power consumption.By using the improved cascade design method,the circuit design,layout drawing and simulation of four analog baseband filters of transceiver are carried out.The receiver's analog baseband filter has a bandwidth tuning range of 200kHz-39.2MHz(1:196),a single pole power consumption of 4.9mW,and a gain adjustment range of 0-33 dB.The design result of the design method presented in this paper is far beyond the research results of related literatures.(3)In view of the problem of the power consumption and large area of the traditional master-slave bandwidth calibration circuit,a digital bandwidth calibration loop is designed,which uses the sampling voltage to compute the equivalent RC of the single pole filter circuit and realizes the filter bandwidth calibration on the main chain.This loop can eliminate the bandwidth calibration error caused by signal transmission delay through the calculation of two times calibration results.Compared with the traditional master-slave bandwidth calibration circuit,this design can reduce the filter layout area and power consumption of approximately 25% in this application.(4)Starting with Sigma-Delta modulator,this paper analyzes the requirement of digital decimation and interpolation filters,introduces the basic principle of digital filter design,discusses the realization structure of digital filter which is suitable for decimation and interpolation filters,and completes the design of digital decimation filters and digital interpolation filters by MATLAB software;In the end,the filter chain of the receiver designed by this paper is modeled and validated.The results show that the filter group of the receiver achieves 100kHz-28 MHz,280 times bandwidth tuning range.Under the application of LTE1.4: band-pass frequency is 0.63 MHz,band-stop frequency is 0.77 MHz,band-pass ripple is 0.025 dB and stop-band suppression is 80.21dB;Under the application of LTE20: band-pass frequency is 9MHz,band-stop frequency is 11 MHz,band-pass ripple is 0.063 dB and stop-band suppression is 80.39 dB.Design results meet the requirements of design specifications,and can be used for programmable RF transceivers.