Programmable Digitalfilterasic Chip Design For Software Defined Radio

This paper studied the high-efficiency digital filter banks for the digital up-conversion and the digital down-conversion in the software radio hardware platform. This digital filters which have natures of center frequency and bandwidth adjustable, occupation less, and implementation easy meats the requirement of Software Defined Radio to handle multi-band, multi-mode, high-speed wideband signals.Dealing with high-speed wideband signals, the traditional directly method of designing the digital filter will result in high order of the filter and therefore a higher complexity which will take up more resources. This paper adopted multi-level structure to design the digital filter banks ----CIC, HB cascaded FIR filters which reduced the complexity. Focus on the requirements for the digital filter whose bandwidth and centre frequency should be adjustable, we proposed a new method ---- adopting interpolation, decimation, and FRM technical to design the FIR digital filter. Based on this method, we could attain a kind of narrow-transition band digital filter, which not only have reconfigurable nature so as to be applied to a variety of communication standard, but also have lower complexity so as to reduce the occupation of the hardware resources, thereby improve the speed of the system. Compared to the traditional method of designing filter, it is verified that this method could save a lot of the hardware resources.In this paper, we firstly figured up the implementation program for each module according to the software-defined radio system, and gave the Matlab simulation of the system. Then we used the Quartus II software for each filter's RTL-level designation, and completed the synthesis simulation. And then, we made the layout design. Finally, we used PADS software to design the hardware circuit board and gave the hardware test results. It is verified that the program is correct.