Research And Design Of High Performance Fully Redundant Decimal Multiplier

Decimal arithmetic units are now in high demand due to the requirement in fields like commercial computing and biomedicine.Decimal multiplier is one of the core computing component in decimal arithmetic,so it is important to design high-performance decimal multipliers.Parallel decimal multipliers consist of three modules: partial products generation,partial products reduction and the final product generation.The arithmetic and circuits for different decimal multipliers are studied in this thesis,and a high-performance 16×16-digit fully redundant decimal multiplier is designed.The main work and achievements are as follow:1.Partial product generation modules based on different BCD codes and multiplier recoding systems are studied and designed.Signed-digit radix-10 recoding and redundant BCD codes is focused on.The circuit for partial product generation module is modified in this thesis.The circuit for multiplicand multipliers based on redundant XS-3 codes is modified in this thesis.2.A new reduction tree based on fully redundant ODDS adders is proposed,and the circuit for this ODDS adder is modified to reduce its complexity.The reduction ratio of ODDS adder is 2:1,the partial product reduction tree based on fully redundant ODDS adders is regular,thus it is easy to implement in very large scale integration.3.Conditional speculative decimal adder and ODDS-BCD recoding module are introduced.The generation of final product for fully redundant decimal multiplier is based on ODDS-BCD recoding module.The 32-digit ODDS-BCD recoding module consists of ODDS-BCD recoders and carry computing units.The carry computing tree and ODDS-BCD recoder have been modified to speed up the ODDS-BCD recoding.4.All the designs are described in Verilog HDL and synthesized by Synopsys Design Compiler.The results achieved with TSMC 65 nm standard-cell show that the performance of the proposed 16×16-digit fully redundant decimal multiplier is faster and requires less hardware area than previous designs found in the technical literature.