Research And Design Of High Performance Decimal Multiplier Using Redundant BCD Codes

Decimal arithmetic is in demand for high accuracy computation in commercial computing,financial analysis,and other applications.There are increasing interests in hardware support for decimal arithmetic due to the new specifications for decimal floating-point arithmetic have been added to the revised IEEE 754-2008 standard.The redundant decimal multiplier mainly includes three key modules: decimal partial product generation,decimal partial product compression and final product generation.In this thesis,the partial product generation circuit of redundant decimal multiplier based on the Signed-Digit Radix-10 recoding,the redundant BCD excess-3 code and the overloaded decimal digit set code is introduced.The Signed-Digit Radix-10 Recoding is used to reduce the number of partial products by half.All partial products can be generated in a carry-free manner by using the redundant BCD excess-3 code,and the negative multiplicand multipliers can be obtained by exploiting the self-complementing property of the redundant BCD excess-3 code.This thesis completes the optimal design of the decimal partial product generation circuit based on the Signed-Digit Radix-10 recoding and redundant BCD excess-3 code.In this thesis,a decimal partial product reduction tree using hybrid BCD codes is proposed;it consists of a binary PPR tree block,a non-fixed size BCD-4221 counter correction block and a BCD-4221/5211 decimal PPR tree block.The binary PPR tree consists of binary 3: 2 compressor and binary 4: 2 compressor,the results of the binary compression are corrected by a correction circuit.This thesis redesigns the decimal partial product compression block by using the method: first generated PPs are compressed firstly,thus improves the performance of the decimal multiplier.The final two partial products are added by a conditional speculative decimal addition to obtain the final product in the final product generation block.All the designs are described in Verilog HDL and synthesized by Synopsys Design Compiler.The results achieved with Nangate Open Cell 45 nm standard-cell show that the performance of the proposed 34×34-digit redundant decimal multiplier is faster and requires less hardware area than previous designs found in the technical literature.