Research And Design Of High Performance Parallel Decimal Multiplier

Hardware supports for decimal arithmetic become more and more important due to the demand of high accuracy computation in commercial computing, financial analysis, and other applications. New specifications for decimal floating-point arithmetic have been added to the revised IEEE 754-2008 standard. The hardware implementation of the decimal arithmetic is becoming a trend and the research on decimal multiplier is a hot spot.The parallel decimal multiplier mainly includes three key modules: decimal partial product generation, decimal partial product compression and final product generation. After in-depth analysis of algorithms and structure of these three modules, a 16×16-digit decimal multiplier based on Signed-Digit Radix-10 Recoding is designed in this thesis. In the decimal partial product generation module, the Signed-Digit Radix-10 Recoding is used to reduce the number of partial products by half, and the proposed speculative decimal adder is used to accelerate the generation of 3X multiples. The decimal compression module accumulates the partial products to two lines by using the reduction tree composed of decimal 3:2 compressor. One digit decimal 3:2 compressor based on BCD-4221 is composed of a 4-bit binary carry save adder and a BCD-4221 to BCD-5211 converter. This thesis redesigns the BCD-4221 recoding circuit by taking the advantage of the redundancy of the BCD-4221 encoding, thus reducing the complexity and delay of reduction tree. At last, the final product generation module uses the proposed conditional speculative decimal adder to quickly get the final product. By analyzing the structure of binary and decimal adders, this paper completes the optimal design of the speculative decimal adder and conditional speculative decimal adder. The characteristics and performance of the two proposed decimal adders are analyzed and applied to the design of parallel decimal multiplier.All the designs are described in Verilog HDL and synthesized by Synopsys Design Compiler. The results achieved with Nangate Open Cell 45 nm standard-cell show that that the performance of the proposed 16×16-digit decimal multiplier based on Signed-Digit Radix-10 Recoding has an effective improvement without area increase.