Research On Accumulation And Quantization Circuit Of TDI CMOS Image Sensor

Time Delay Integration(TDI)CMOS image sensor can achieve sub-pixel image information sampling by increasing the sampling rate and integral accumulation,and attention has been paid to the field of line array image sensors.The sampling rate,accumulating circuit and quantization circuit performance directly affect the imaging quality of TDI image sensor.The research on the accumulation and quantization circuit based on TDI CMOS image sensor is of great significance to improve the imaging quality and signal-to-noise ratio of scanned images.Aiming at the performance requirements of the image acquisition system of the lensless cell imaging system,based on the analysis of the imaging mechanism of the TDI CMOS image sensor,the imaging process and image restoration effect of the TDI CMOS image sensor are simulated.Through simulation,comparing the image reduction effects of different sampling frequencies and accumulated stages,according to the application characteristics of the lensless cell image acquisition system,the cumulative number of stages is determined.On this basis,the circuit structure of the analog accumulator with adjustable sampling rate and cumulative number of stages is given and the design and simulation of the circuit are completed.The accumulator is implemented based on the principle of charge accumulation,and the circuit module is composed of an op amp and a capacitor network.Through the timing control,multiple accumulation sampling is completed.In order to increase the output voltage swing,reduce the circuit noise,and suppress the interference of the digital circuit and the clock drive circuit,the main operational amplifier design of the accumulator adopts a fully differential folded cascode structure.Since the accumulator output is a differential signal,this paper designs a 10-bit dual-slope analog-to-digital converter(ADC)with a fully differential structure.The circuit consists of a dual ramp generator and a comparator.The ramp generator is based on the structure of the current rudder,implemented with a 3-bit binary code plus a 7-digit thermometer code.The comparator is implemented using a three-stage pre-amplification dynamic structure.The 8-level TDI accumulator and the fully differential dual-slope ADC were designed and simulated based on SMIC 0.18 ?m CMOS process,and the layout and post-simulation of the circuit were further carried out.The results show that the accumulated result of the accumulator differs from the theoretical value by less than 0.88mV,and the error satisfies the accuracy requirement of the calculated LSB/2.The quantized voltage range of the column ADC is 0-1.8 V.The input sinusoidal signal of 1.6942 kHz is sampled at a sampling frequency of 19.49 kS/s,and the signal-to-noise ratio is about 60.9 dB,and the spurious-free dynamic range is about 78.39 dB.The effective number of bits is 9.6-bit,which meets the system design requirements.