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Research Of Accumulator In High-stage CMOS-TDI Image Sensors

Posted on:2015-02-28Degree:MasterType:Thesis
Country:ChinaCandidate:F J HuangFull Text:PDF
GTID:2348330485496055Subject:Integrated circuit engineering
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Time Delay Integrator(TDI) image sensor is a special linear array image sensor. Because of the the advantages of linear array image sensor, high sensitivity and high imaging quality, TDI image sensor has been widely applied in satellite remote sensing, medical imaging and etc high-tech field. Currently research results about TDI image sensor mainly focus on charge coupled device(CCD), and the research on CMOS TDI image sensor(TDI CIS) research is less. Based on the principle of the traditional analog accumulator of TDI CIS, this paper has researched and designed the accumulator in high-stage TDI CIS.First of all, comparing several exposure modes which are suitable for TDI image sensor, system structure of TDI CIS is proposed, and the principle of the accumulator high-stage TDI CIS is discussed. Second, based on the parasitic source, the influence in sample and integration phase and the result of modeling simulation, the reason for the limitaions in effective accumulation of traditional analog accumulator is analyzed and expounded. Then three methods for solve the parasitic effects is proposed: adding decoupling switch to cut down the parasitism of integrator in integration phase, compensating the parasitism which can not be eliminated by top plate sampling technique, compensating the parasitism which can not be eliminated by positive feedback capacitance. Based on the proposed methods, two 128-stage analog accumulator schemes which are suitable for high-stage TDI CIS are designed. Finally, the circuits of the improved schemes and the layout are planed, and through extracting the layout parasitic netlist, post simulation is completed to verify the structure.The ideal value of the improved SNR in a 128-stage analog accumulator is 21.072 dB, while according to the post simulation results, the improved SNR of two structures are 21.066 dB and 21.068 dB, respectively, and the linearitys are 99.62% and 99.7%, respectively. In order to verify the stability, the Monte Carlo simulations and two kinds of extreme case simulations about two structures are completed. The results show that in all cases, the improved SNR in proposed structures are over 21.05 dB.
Keywords/Search Tags:Accumulator, Signal-to-noise Ratio, Time Delay Integration, CMOS image sensor
PDF Full Text Request
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