Research And Design Of High Stage And High Speed CMOS-TDI Image Sensor

Time-delay-integration(TDI) image sensor is a special kind of multiline line-array image sensor, which works in scanning mode. TDI image sensor can extend exposure time and improve SNR by Adding the pixel signal along the motion direction of image sensor. Therefore, TDI image sensor is especially suitable in the situation of low illumination and high relative speed, for example, space imaging, medical imaging and industrial monitoring. With the development of CMOS technology, the advantages of CMOS TDI image sensor such as low power and highly integration are more obvious. However, tow problems still remain, restricting the developing of TDI image sensor, one of which is realizing the high stage of TDI, the other is realizing the high readout speed. This paper is focused on TDI image sensor high stage, high speed design and tape-out, based on system architecture and readout circuit design of TDI image sensor.A new exposure method based on the Along-Track-Rolling shutter with time-under-sampling is proposed, which can optimize the synchronism and readout speed of the signal and reduce the integrator needed by accumulator, combined with pixel grouping exposure method. Based on the analysis of the circuit architecture and non-ideal effects in CMOS-TDI image sensor, 32 row 1024 column CMOS-TDI image sensor architecture with a decoupling capacitor to alleviate parasitic effects is proposed in this thesis. Then, based on the Along-Track-Rolling shutter with time-under-sampling, a two-step accumulator structure is proposed to reduce the parasitic effects, which can improve the equal stage dramatically. Taking advantage of the two-stage structure and the decoupling method, two versions of 64-stage two-step accumulators with time-under-sampling Along-Track-Rolling shutter are designed and fabricated, which can further improve the equal stage. Simulation results show that the highest equal stage can be improved to 1000 from 200. A pipelined sampling accumulator structure is presented in this paper, which combined both the op-amp sharing technique and the pipeline sampling technique. Thus, the accumulator speed is doubled without extra power or area consumption. It achieves 2MS/s with only 0.29 mW power dissipation at 3.3V voltage supply and 1MHz clock.Based on the research above, a 32×1024 analog accumulator CMOS-TDI image sensor chip is fabricated in GSMC 0.18 um CMOS process, chip area is 214mm2. Test results show that the equal stage of the 32-stage analog accumulator with decoupling capacitor is 26.387. Furthermore, two versions of 64-stage two-step analog accumulators are fabricated in GSMC 0.18 um CMOS process, chip area is 4.2mm2. Test results show that the 64-stage two-step analog accumulator with decoupling capacitor can achieve 4.9 equal stage increase than one step method and 2.2 equal stage increase than decoupling version.