Implementation And Verification Of G.729 Speech Decoding Algorithm Based On FPGA

With the rapid development of the information society,the deamnd for performance of speech codecs are getting higher and higher.The G.729 voice codec algorithm has become the major solution because of the advantage of low latency,low code rate,and high-quality voice.However,speech processing based on traditional DSPs always have some performance bottlenecks because of the high algorithm complexity and large data storage capacity.Therefore,the thesis seeks to acomplish the hardware implementation and verification of G.729 speech decoder based on FPGA.Firstly,the basic principle of the G.729 speech decoding algorithm is discussed in the thesis,and then the correctness of the G.729 algorithm is verified on Visual Studio.On this basis,the implementation of the G.729 decoder IP core is achieved with high level synthesis(HLS)design method.The design is completed following HLS design flow,after modification,simulation verification,synthesis,co-simulation and IP encapsulation of C code on Vivado HLS platform.The result shows that the average system delay of one frame data processing is only 0.4ms,much less than the DSP implementation.In order to simulate FPGA verification on the G.729 decoder IP core,an IP core peripheral test circuit is built to constitute a G.729 decoder IP core verification system.In view of the limited system performance optimization scheme under the high-level synthesis design method,the hardware design of the linear prediction filter parametric decoding system,speech reconstruction and post-processing filters of the G.729 speech decoding algorithm is completed with the hardware description language(HDL)design method.The design method and working process are discussed in detail in the thesis.The linear prediction filter parametric decoding system is divided into the following five modules:lsp top module and cb_cearch,lsp_expand,lsp_prev_compose,lsf2 lsp submodules.To improve system performance,the above modules are optimized in many ways.The result shows that system resource occupation and average delay with HDL design method are less than half of the implementation with HLS design method.The functional simulation of each module and system is processed using Vivado Simulator.The hardware verification of G.729 decoder IP core verification system and linear prediction filter parametric decoding system is performed on the KC705 FPGA development board.The correctness of the hardware system function is verified due to the consistent hardware and software simulation results.